MC74F148N ,8-LINE TO 3-LINE PRIORITY ENCODER FAST SHOTTKY TTLMC54/74F1488-LINE TO 3-LINEPRIORITY ENCODERThe MC54/74F148 provides three bits of binary coded outp ..
MC74F14D ,SCHMITT TRIGGERS DUAL 4-INPUT NAND/HEX INVERTERS FAST SCHOTTKY TTL
MC74F153D ,DUAL 4-INPUT MULTIPLEXERMC54/74F153DUAL 4-INPUT MULTIPLEXERThe MC54/74F153 is a high-speed Dual 4-Input Multiplexer with co ..
MC74F153N ,DUAL 4-INPUT MULTIPLEXERMC54/74F153DUAL 4-INPUT MULTIPLEXERThe MC54/74F153 is a high-speed Dual 4-Input Multiplexer with co ..
MC74F157A ,QUAD 2-INPUT MULTIPLEXER
MC74F157AD ,Quad 2-input multiplexer
MCP809M3-2.63 ,3-Pin Microprocessor Reset CircuitsPin DescriptionPIN NAME FUNCTION3 GND Ground referenceActive-low output. RESET remains low while V ..
MCP809M3-2.93 ,3-Pin Microprocessor Reset CircuitsPin DescriptionPIN NAME FUNCTION3 GND Ground referenceActive-low output. RESET remains low while V ..
MCP809M3-3.08 ,3-Pin Microprocessor Reset CircuitsPin DescriptionPIN NAME FUNCTION3 GND Ground referenceActive-low output. RESET remains low while V ..
MCP809M3-4.38 ,3-Pin Microprocessor Reset CircuitsFeaturesn Precise monitoring of 3V, 3.3V, and 5V supply voltagesThe MCP809/810 microprocessor super ..
MCP809M3-4.63 ,3-Pin Microprocessor Reset CircuitsPin DescriptionPIN NAME FUNCTION3 GND Ground referenceActive-low output. RESET remains low while V ..
MCP809M3X-2.63 ,3-Pin Microprocessor Reset CircuitsApplicationsactive-low RESET output, while the MCP810 has ann Microprocessor Systemsactive-high RES ..
MC74F148N
8-LINE TO 3-LINE PRIORITY ENCODER FAST SHOTTKY TTL
8-LINE TO 3-LINE
PRIORITY ENCODERThe MC54/74F148 provides three bits of binary coded output representing
the position of the highest order active input, along with an output indicating
the presence of any active input. It is easily expanded via input and output en-
ables to provide priority encoding over many bits. Encodes Eight Data Lines in Priority Provides 3-Bit Binary Priority Code Input Enable Capability Signals When Data Present on Any Input Cascadable for Priority Encoding of n Bits
CONNECTION DIAGRAM DIP (TOP VIEW)VCC GS I3 I2 I1 I0 A0 I5 I6 I7 E1 A2 A1 GND
NOTE:
This diagram is provided only for the understanding of logic operations and should not
LOGIC DIAGRAM(10)
(5)
(15)
(9)
(7)
(6)
