MC74F112N ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
MC74F112N ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
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MC74F112N
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOPThe MC74F112 contains two independent, high-speed JK flip-flops with Di-
rect Set and Clear inputs. Synchronous state changes are initiated by the fal-
ling edge of the clock. Triggering occurs at a voltage level of the clock and is
not directly related to the transition time. The J and K inputs can change when
the clock is in either state without affecting the flip-flop, provided that they are
in the desired state during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD
force both Q and Q HIGH.
SD1
GNDCP1 J1K1 Q1 Q1 Q2
CONNECTION DIAGRAMVCC CD1 CD2 CP2 J2 Q2
SD2K2
FUNCTION TABLE (Each Half)L = LOW Voltage Level
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse