MC74AC74DTR2 ,Dual D-Type Positive Edge Trigger3MC74AC74, MC74ACT74AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semicon ..
MC74AC74MEL ,Dual D-Type Positive Edge Triggerpositive edge of the clock pulse. Clock triggering occurs at a voltagelevel of the clock pulse and ..
MC74AC74N ,DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP * DUAL D-TYPE POSITIVEEDGE-TRIGGEREDThe MC74AC74/74ACT74 is a dual D-type flip-flop with Asynch ..
MC74AC74N ,DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOPMAXIMUM RATINGS*Symbol Parameter Value UnitV DC Supply Voltage (Referenced to GND) –0.5 to +7.0 VCC ..
MC74AC74N ,DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP * DUAL D-TYPE POSITIVEEDGE-TRIGGEREDThe MC74AC74/74ACT74 is a dual D-type flip-flop with Asynch ..
MC74AC74N ,DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP * DUAL D-TYPE POSITIVEEDGE-TRIGGEREDThe MC74AC74/74ACT74 is a dual D-type flip-flop with Asynch ..
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MC74AC74-MC74AC74DR2-MC74AC74DTR2-MC74AC74MEL-MC74ACT74-MC74ACT74D-MC74ACT74DR2-MC74ACT74MEL-MC74ACT74N
Dual D-Type Positive Edge Trigger
MC74AC74, MC74ACT74
Dual D-Type Positive
Edge-Triggered Flip-Flop
The MC74AC74/74ACT74 is a dual D–type flip–flop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is locked out and
information present will not be transferred to the outputs until the
next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH Outputs Source/Sink 24 mA ′ACT74 Has TTL Compatible Inputs
VCC
CD1 D1 CP1 SD1 Q1 Q1
CD2 D2 CP2 SD2 Q2 Q2
GND
Figure 1. Pinout: 14–Lead Packages Conductors(Top View)
PIN ASSIGNMENT
