MC74AC377DWR2 ,Octal D Flip-Flop with Clock Enablethe Clock Enable (CE) is LOW. The register is fully edge-triggered.The state of each D input, one s ..
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MC74AC377N ,OCTAL D FLIP-FLOP WITH CLOCK ENABLELOGIC DIAGRAMD D D D D D D D0 1 2 3 4 5 6 7CED Q D Q D Q D Q D Q D Q D Q D QCP CP CP CP CP CP CP CP ..
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MC74AC377DWR2-MC74AC377N
Octal D Flip-Flop with Clock Enable
MC74AC377, MC74ACT377
Octal D Flip-Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation. Ideal for Addressable Register Applications Clock Enable for Address and Data Synchronization Applications Eight Edge-Triggered D Flip-Flops Buffered Common Clock Outputs Source/Sink 24 mA See MC74AC273 for Master Reset Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version ACT377 Has TTL Compatible Inputs MSL = 1 for all Surface Mount Chip Complexity: 292 FETs or 73 Gates
