MC74ACT161N ,Presetable Binary CounterLOGIC DIAGRAMP P P P0 1 2 3PE′161 ′163CEPCET′163ONLYTCCP CP ′161CPONLYD CP DCDQ QDETAIL A DETAIL A ..
MC74ACT163 ,MONO I/C Synchronous Preset Binaryhttp://onsemi.com3MC74AC161, MC74ACT161, MC74AC163, MC74ACT163RECOMMENDED OPERATING CONDITIONSSymbo ..
MC74ACT163DR2 ,MONO I/C Synchronous Preset BinaryMC74AC161, MC74ACT161,MC74AC163, MC74ACT163Synchronous PresettableBinary CounterThe MC74AC161/74ACT ..
MC74ACT163N ,SYNCHRONOUS PRESETTABLE BINARY COUNTERLOGIC DIAGRAMP P P P0 1 2 3PE′161 ′163CEPCET′163ONLYTCCP CP ′161CPONLYD CP DCDQ QDETAIL A DETAIL A ..
MC74ACT163N ,SYNCHRONOUS PRESETTABLE BINARY COUNTERMAXIMUM RATINGS*Symbol Parameter Value UnitV DC Supply Voltage (Referenced to GND) –0.5 to +7.0 VCC ..
MC74ACT163N ,SYNCHRONOUS PRESETTABLE BINARY COUNTERFUNCTIONAL DESCRIPTIONThe MC74AC161/74ACT161 and MC74AC163/74ACT163 (′161) or SR (′163) HIGH, CEP a ..
MCP2551 , High-Speed CAN Transceiver
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP6002-I/MS , 1 MHz Bandwidth Low Power Op Amp
MCP6002I/SN , 1 MHz Bandwidth Low Power Op Amp
MC74AC161N-MC74AC163N-MC74ACT161D-MC74ACT161N-MC74ACT163N
SYNCHRONOUS PRESETTABLE BINARY COUNTER
--The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high-speed
synchronous modulo-16 binary counters. They are synchronously presettable for
application in programmable dividers and have two types of Count Enable inputs
plus a Terminal Count output for versatility in forming synchronous multistage
counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input
that overrides all other inputs and forces the outputs LOW. The MC74AC163/
74ACT163 has a Synchronous Reset input that overrides counting and parallel
loading and allows the outputs to be simultaneously reset on the rising edge of
the clock. Synchronous Counting and Loading High-Speed Synchronous Expansion Typical Count Rate of 125 MHz Outputs Source/Sink 24 mA ′ACT161 and ′ACT163 Have TTL Compatible Inputs
VCC Q0 Q1 Q2 Q3 CET PE CP P0 P1 P2 P3 CEP GND
PIN NAMESCEP Count Enable Parallel Input
CET Count Enable Trickle Input Clock Pulse Input (′161) Asynchronous Master Reset Input (′163) Synchronous Reset Input
P0–P3 Parallel Data Inputs Parallel Enable Input
Q0–Q3 Flip-Flop Outputs Terminal Count Output
LOGIC SYMBOL*MR for ′161
*SR for ′163
