MC74HCT374ADW ,Octal 3-State Non-Inverting Flip-Flop**SEMICONDUCTOR TECHNICAL DATA*#** #*#* **%*!#* * &*#*J SUFFIX *#* ** $#"CERAMIC PACKAGE20CASE 73 ..
MC74HCT374ADWR2 ,Octal 3-State Non-Inverting Flip-FlopThe MC74HCT374A may be used as a level converter forinterfacing TTL or NMOS outputs to High–Speed C ..
MC74HCT374AF ,Octal 3-State NonInverting D Flip-Flop with LSTTL Compatible InputsELECTRICAL CHARACTERISTICS (V = 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)CC L r fÎGuaranteed Li ..
MC74HCT374AF ,Octal 3-State NonInverting D Flip-Flop with LSTTL Compatible InputsMAXIMUM RATINGS*ÎÎÎÎÎÎ Symbol ParameterÎÎÎÎÎ ValueÎÎÎ UnitThis device contains protectioncircuitry ..
MC74HCT374AFL1 ,Octal 3-State NonInverting D Flip-Flop with LSTTL Compatible InputsELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎGuaranteed LimitÎV – 55 toCCVÎÎÎ SymbolÎÎ ..
MC74HCT374AFL1 ,Octal 3-State NonInverting D Flip-Flop with LSTTL Compatible InputsThe MC74HCT374A may be used as a level converter forinterfacing TTL or NMOS outputs to High–Speed C ..
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MC54HCT374AJ-MC74HCT374ADW-MC74HCT374AN
Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs
SEMICONDUCTOR TECHNICAL DATA## %!# &#
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High–Performance Silicon–Gate CMOSThe MC54/74HCT374A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with the
rising edge of Clock. The Output Enable does not affect the state of the
flip–flops, but when Output Enable is high, the outputs are forced to the
high–impedance state. Thus, data may be stored even when the outputs
are not enabled.
The HCT374A is identical in function to the HCT574A, which has the
input pins on the opposite side of the package from the output pins. This
device is similar in function to the HCT534A, which has inverting outputs. Output Drive Capability: 15 LSTTL Loads TTL/NMOS–Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 μA In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 276 FETs or 69 Equivalent Gates Improvements over HCT374 Improved Propagation Delays 50% Lower Quiescent Power Improved Input Noise and Latchup Immunity
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LOGIC DIAGRAMDATA
INPUTSCLOCK18OUTPUT ENABLE
NONINVERTING
OUTPUTS
