MC74HCT373AN ,Octal LatchMAXIMUM RATINGS*Symbol Parameter Value UnitThis device contains protectionÎÎÎcircuitry to guard aga ..
MC74HCT374ADW ,Octal 3-State Non-Inverting Flip-Flop**SEMICONDUCTOR TECHNICAL DATA*#** #*#* **%*!#* * &*#*J SUFFIX *#* ** $#"CERAMIC PACKAGE20CASE 73 ..
MC74HCT374ADWR2 ,Octal 3-State Non-Inverting Flip-FlopThe MC74HCT374A may be used as a level converter forinterfacing TTL or NMOS outputs to High–Speed C ..
MC74HCT374AF ,Octal 3-State NonInverting D Flip-Flop with LSTTL Compatible InputsELECTRICAL CHARACTERISTICS (V = 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)CC L r fÎGuaranteed Li ..
MC74HCT374AF ,Octal 3-State NonInverting D Flip-Flop with LSTTL Compatible InputsMAXIMUM RATINGS*ÎÎÎÎÎÎ Symbol ParameterÎÎÎÎÎ ValueÎÎÎ UnitThis device contains protectioncircuitry ..
MC74HCT374AFL1 ,Octal 3-State NonInverting D Flip-Flop with LSTTL Compatible InputsELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎGuaranteed LimitÎV – 55 toCCVÎÎÎ SymbolÎÎ ..
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MC54HCT373AJ-MC74HCT373AN
Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs
SEMICONDUCTOR TECHNICAL DATA!! #! ! ! $!"!
High–Performance Silicon–Gate CMOSThe MC54/74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent D–type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs. When
Latch Enable is taken low, data meeting the setup and hold times
becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high–impedance state.
Thus, data may be latched even when the outputs are not enabled.
The HCT373A is identical in function to the HCT573A, which has the
input pins on the opposite side of the package from the output pins. This
device is similar in function to the HCT533A, which has inverting outputs. Output Drive Capability: 15 LSTTL Loads TTL/NMOS–Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 μA In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 196 FETs or 49 Equivalent Gates
LOGIC DIAGRAMDATA
INPUTS18OUTPUT ENABLE
PIN 20 = VCC
PIN 10 = GND
NONINVERTING
OUTPUTSLATCH ENABLE