MC74HCT245ADW ,Octal 3-State Non-Inverting TransceiverMAXIMUM RATINGS*Symbol Parameter Value UnitThis device contains protectionÎÎÎcircuitry to guard aga ..
MC74HCT245ADWR2 ,Octal 3-State Non-Inverting Transceiveroutputs to High Speed CMOS inputs.The MC74HCT245A is a 3–state noninverting transceiver that isMARK ..
MC74HCT245AF ,Octal 3-State NonInverting Bus Transceiver with LSTTL Compatible InputsELECTRICAL CHARACTERISTICS (V = 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)CC L r fÎÎÎÎÎ Guarante ..
MC74HCT245AFL1 ,Octal 3-State NonInverting Bus Transceiver with LSTTL Compatible InputsELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎGuaranteed LimitÎÎÎV– 55 toCCÎVSymbol ..
MC74HCT245AN ,Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs**SEMICONDUCTOR TECHNICAL DATA*#** #*#* **%*!#*$" !**"%*! * &*#*J SUFFIX** *#* ** $#"CERAMIC PACKA ..
MC74HCT245AN ,Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible InputsELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitÎÎÎV V– 55 toÎÎÎ CCÎÎÎÎÎVSym ..
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MC54HCT245AJ-MC74HCT245ADW-MC74HCT245AN
Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs
SEMICONDUCTOR TECHNICAL DATA## %!#
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High–Performance Silicon–Gate CMOSThe MC54/74HCT245A is identical in pinout to the LS245. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
The MC54/74HCT245A is a 3–state noninverting transceiver that is
used for 2–way asynchronous communication between data buses. The
device has an active–low Output Enable pin, which is used to place the
I/O ports into high–impedance states. The Direction control determines
whether data flows from A to B or from B to A. Output Drive Capability: 15 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 μA In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 304 FETs or 76 Equivalent Gates
LOGIC DIAGRAMDATA
PORT
DIRECTION
OUTPUT ENABLE PIN 20 = VCC
PIN 10 = GND
DATA
PORT
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ Equivalent to a two–input NAND gate.
FUNCTION TABLE
