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MC54HC259J-MC74HC259-MC74HC259N
8-Bit Addressable Latch 1-of-8 Decoder
SEMICONDUCTOR TECHNICAL DATA !-
High–Performance Silicon–Gate CMOSThe MC54/74HC259 is identical in pinout to the LS259. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC259 has four modes of operation as shown in the mode selection
table. In the addressable latch mode, the data on Data In is written into the
addressed latch. The addressed latch follows the data input with all
non–addressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous state and are unaffected by the
Data or Address inputs. In the one–of–eight decoding or demultiplexing
mode, the addressed output follows the state of Data In with all other outputs
in the LOW state. In the Reset mode all outputs are LOW and unaffected by
the address and data inputs. When operating the HC259 as an addressable
latch, changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the memory
mode. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 202 FETs or 50.5 Equivalent Gates
LOGIC DIAGRAMADDRESS
INPUTS
DATA IN
RESET
ENABLEQ0
PIN 16 = VCC
PIN 8 = GND
NONINVERTING
OUTPUTS
