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MC33565DR2-MGSF1P02ELT1
Smart Voltage Regulator for Peripheral Card Applications
AN1686/D
Intelligent LDO Regulator
with External Bypass
Control
Prepared by: Lonne Mays
Introduction
Glitch-Free Supply Transition from the 5 V primary
supply to the auxiliary 3.3 V supply can be easily
implemented for PCI/NIC and other motherboard slot cards
via the MC33565 Intelligent LDO regulator. This linear
regulator contains detection and logic circuitry to determine
which supply is active and take appropriate action to
maintain a steady 3.3 V output, even as the supply planes
change from “working” state to “system sleep” state.
The Advanced Configuration and Power Interface
(ACPI) design specification for managing powerconsumption within PC’s provides for various power
consumption states from G0 (CPU actively executing code)
to four different levels (S1-S4) within the G1 sleep state. The
system can be roused from the various levels of the sleep
state without requiring a reboot of the Operating System
because both the system hardware and software save large
elements of the system context. To be ACPI compliant,
Network Cards and modems plugged into the motherboard
should be designed to function both from the 5 V main
supply plane (available in G0 state) and the auxiliary 3.3 V
supply (available in G1 state).
ACPI compliant systems can provide important benefits
to the end-user, including: PC’s appear “off” and quiet when not actively in use,
but resume full operation when required. Network communication can be received by an ACPI
compliant card even though the PC is in sleep state. Energy efficient operation without inconveniencing the
end-user.1
The MC33565 Intelligent LDO has been developed to
provide the hardware designer a convenient and easy
implementation of the dual supply compliance.
An External Bypass MOSFET is controlled by theMC33565 to connect the 3.3 V auxiliary supply directly to
the output, thus bypassing the internal linear low dropout
regulator whenever the 5 V main supply is not present.
When the 5 V main supply power is present, the internal
LDO circuitry regulates this down to 3.3 V and provides it
to the output at currents up to 200 mA (the bypass
MOSFET’s gate is biased “off” at this time). The internal
5 V detection and logic circuitry has sufficient hysteresis to
prevent inappropriate toggling between the two supplies if
a full load is suddenly applied. (Note: this requires that the
source impedance of the 5 V supply, including wiring and
printed circuit trace DCR, be less than 0.25 ohm for 200 mA
loads.)
Power Dissipation of the MC33565, when mountedappropriately on conventional FR4 epoxy PCB, is sufficient
to support regulation of the 5 V input down to 3.3 V at an
output current of 200 mA. The power dissipated by the
external bypass P-channel MOSFET is a function of its
Rds(on). The dissipation is trivial with the recommended
MGSF1P02ELT1 SOT-23 packaged MOSFET which has a
typical Rds(on) of 400 milliohms at Vgs = 2.5 V. P-channel
MOSFETs with similar or lower Rds(on) and gate sensitivity
parameters should work as well.
The MC33565 device contains 121 active transistors
comprising the following functions: Low dropout regulator Internal voltage reference and 5 V detection circuitry Voltage compensation and hysteresis control Voltage comparator and MOSFET gate driver
Figure 1 depicts the functional relationships in block
diagram form. Note that the 3.3 Vin is an input to both the
MC33565 and to the drain of the external P-channel
MOSFET. The 3.3 V
regulation from the +5 Vin input, or else is simply passed
directly from the +3.3 Vin input to the +3.3 V
gating on the external MOSFET which then acts as a bypass
switch around the LDO.
