MC26LS30DR2 ,Dual Differential (EIA-422-A)/Quad Single-Ended (EIA-423-A) Line Drivers3MC26LS30
MC26LS30DR2 ,Dual Differential (EIA-422-A)/Quad Single-Ended (EIA-423-A) Line Drivers2MC26LS30
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MC74HC00AF ,Quad 2-Input NAND GateMaximum ratingsapplied to the device are individual stress limit values (not normal operating condi ..
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MC74HC00AN ,Quad 2-Input NAND GateOrder this documentMOTOROLA by AN1319/DSEMICONDUCTORAPPLICATION NOTE ** * * ** ** **Prepared by: W ..
mc74HC02 ,Quad 2-Input NOR GateMAXIMUM RATINGS*ÎÎÎÎÎÎ Symbol ParameterÎÎÎÎÎ ValueÎÎÎ UnitThis device contains protectioncircuitry ..
MC74HC02A ,Quad 2-Input NOR GateELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)L r fGuaranteed LimitÎÎV – 55 toCCÎÎÎÎÎ ..
MC26LS30-MC26LS30D-MC26LS30DR2
Dual Differential (EIA-422-A)/Quad Single-Ended (EIA-423-A) Line Drivers
MC26LS30
Dual Differential
(EIA-422-A)/
Quad Single-Ended
(EIA-423-A) Line Drivers
The MC26LS30 is a low power Schottky set of line drivers which
can be configured as two differential drivers which comply with
EIA–422–A standards, or as four single–ended drivers which comply
with EIA–423–A standards. A mode select pin and appropriate choice
of power supplies determine the mode. Each driver can source and
sink currents in excess of 50 mA.
In the differential mode (EIA–422–A), the drivers can be used up to Mbaud. A disable pin for each driver permits setting the outputs
into a high impedance mode within a +10 V common mode range.
In the single–ended mode (EIA–423–A), each driver has a slew rate
control pin which permits setting the slew rate of the output signal so
as to comply with EIA–423–A and FCC requirements and to reduce
crosstalk. When operated from symmetrical supplies (+5.0 V), the
outputs exhibit zero imbalance
The MC26LS30 is available in a 16–pin surface mount package.
Operating temperature range is –40° to +85°C. Operates as Two Differential EIA–422–A Drivers, or Four
Single–Ended EIA–423–A Drivers High Impedance Outputs in Differential Mode Short Circuit Current Limit In Both Source and Sink Modes ±10 V Common Mode Range on High Impedance Outputs ±15 V Range on Inputs Low Current PNP Inputs Compatible with TTL, CMOS, and MOS
Outputs Individual Output Slew Rate Control in Single–Ended Mode Replacement for the AMD AM26LS30 and National Semiconductor
DS3691
Representative Block Diagrams
Single–Ended Mode
EIA–423–A
Differential Mode
EIA–422–AEnable CD
Enable AB
Out D
Out C
Out B
Out A
VCC�-�1
VEE�-�8
Input D
Input A
Input A
SR-A
Out A
Gnd�-�5
Mode�-�4
SR-B
SR-C
Out D
SR-D
Out C
Out BInput B
Input C
Input D
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ORDERING INFORMATION
PIN CONNECTIONSInput C/
Enable CD
(Top View)
SR-A
Output A
Output B
Input D
VEE SR-D
Output D
Output C
SR-C
SR-B
Gnd
VCC
Input A
Mode
Input B/
Enable AB
SO–16
D SUFFIX
CASE 751B16 1
MARKING
DIAGRAM = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
