MC14526B ,Presettable 4-Bit Down Counters3MC14526B(7.)ÎÎÎÎÎ SWITCHING CHARACTERISTICS (C = 50 pF, T = 25C)L A(8.)ÎÎÎÎÎ Characteristic Symb ..
MC14526B ,Presettable 4-Bit Down CountersMaximum Ratings are those values beyond which damage to the deviceMC14526BF SOEIAJ–16 See Note 1.ma ..
MC14526BCL ,Presettable 4-bit down counterMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
MC14526BCL ,Presettable 4-bit down counter**SEMICONDUCTOR TECHNICAL DATA** * * * * **The MC14522B BCD counter and the MC14526B binary counte ..
MC14526BCP ,Presettable 4-bit down counterMAXIMUM RATINGS* (Voltages Referenced to V )SSMC14XXXBDW SOICSymbol Parameter Value UnitT = – 55° t ..
MC14527BCL ,BCD Rate MultiplierMaximum Ratings are those values beyond which damage to the device may occur. SÎÎÎ12 7CASC Eout†Tem ..
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MC14526B
Presettable 4-Bit Down Counters
MC14526B
Presettable 4-Bit Down
Counters
The MC14526B binary counter is constructed with MOS P–channel
and N–channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide–by–N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide–by–N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phase–locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity. Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Edge–Clocked Design — Incremented on Positive Transition
of Clock or Negative Transition of Inhibit Asynchronous Preset Enable Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Maximum Ratings are those values beyond which damage to the device
may occur. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
