MC14508BCL ,Dual 4-Bit LatchMAXIMUM RATINGS* (Voltages Referenced to V )ORDERING INFORMATIONSSSymbol Parameter Value Unit MC14X ..
MC14508BCL ,Dual 4-Bit LatchMaximum Ratings are those values beyond which damage to the device may occur.2 ST†Temperature Derat ..
MC14508BCP ,Dual 4-Bit LatchMaximum Ratings are those values beyond which damage to the device may occur.2 ST†Temperature Derat ..
MC145100CP ,4 X 4 CROSSPOINT SWITCH WITH CONTROL MEMORYMCI42100MOTOROLA MC1451004 X 4 CROSSPOINT SWITCH WITH CONTROL MEMORYThe MC142100 and MC145100consis ..
MC145106P ,PLL Frequency SynthesizerMAXIMUM RATINGS (Voltages Referenced to V )SSThis device contains circuitry to protect theParameter ..
MC14510BCL ,BCD Up/Down Counter**SEMICONDUCTOR TECHNICAL DATA** * *The MC14510B synchronous up/down BCD counter is constructed wit ..
MC68HC711E20MFN2 ,Microcontroller, 2 MHz, RAM=768, ROM=0, EPROM=20K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E20VFN2 ,Microcontroller, 2 MHz, RAM=768, ROM=0, EPROM=20K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E9CFN2 ,Microcontroller, 2 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E9CFN3 ,Microcontroller, 3 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E9CFN3 ,Microcontroller, 3 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E9CFN3 ,Microcontroller, 3 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC14508BCL-MC14508BCP
Dual 4-Bit Latch
-The MC14508B dual 4–bit latch is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure. The
part consists of two identical, independent 4–bit latches with separate Strobe
(ST) and Master Reset (MR) controls. Separate Disable inputs force the
outputs to a high impedance state and allow the devices to be used in time
sharing bus line applications.
These complementary MOS latches find primary use in buffer storage,
holding register, or general digital logic functions where low power
dissipation and/or high noise immunity is desired. 3–State Output Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable–of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
TRUTH TABLEX = Don’t CareDIS
VDD
SEMICONDUCTOR TECHNICAL DATA
