MC14076B ,4-Bit D-Type Register with Three-State OutputsELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ − 55CÎÎ 25CÎÎÎÎÎ 125CÎÎÎV VDDChar ..
MC14076BCL ,4-Bit D-Type Register with Three-State Outputs** ** * SEMICONDUCTOR TECHNICAL DATA** " * * !** **L SUFFIX ** *CERAMICCASE 620The MC14076B 4–B ..
MC14076BCL ,4-Bit D-Type Register with Three-State OutputsBLOCK DIAGRAMÎÎÎÎÎV DC Supply Voltage – 0.5 to + 18.0 VDDRESET Q015 3ÎÎV , V Input or Output Voltag ..
MC14076BCP ,4-Bit D-Type Register with Three-State OutputsMaximum Ratings are those values beyond which damage to the device may occur.ÎÎÎ2 B OUTPUT†Temperat ..
MC14077B ,Quad Exclusive NOR GateFeatures14• Supply Voltage Range = 3.0 Vdc to 18 VdcPDIP−14• All Outputs Buffered MC140xxBCPP SUFFI ..
MC14077BAL ,CMOS SSI Quad Exclusive "OR" and "NOR" GatesMAXIMUM RATINGS* (Voltages Referenced to V ) SOICSSCASE 751AÎÎSymbol Parameter Value UnitÎÎÎÎÎV DC ..
MC68EC020FG16 ,MICROPROCESSORS USERS MANUALMC68020MC68EC020MICROPROCESSORSUSER’S MANUALFirst EditionMotorola reserves the right to make change ..
MC68EC020FG25 ,MICROPROCESSORS USERS MANUALMC68020MC68EC020MICROPROCESSORSUSER’S MANUALFirst EditionMotorola reserves the right to make change ..
MC68EC020RP16 ,MICROPROCESSORS USERS MANUALMC68020MC68EC020MICROPROCESSORSUSER’S MANUALFirst EditionMotorola reserves the right to make change ..
MC68EC020RP25 ,MICROPROCESSORS USERS MANUALMC68020MC68EC020MICROPROCESSORSUSER’S MANUALFirst EditionMotorola reserves the right to make change ..
MC68EC020RP-25 ,MICROPROCESSORS USERS MANUALMC68020MC68EC020MICROPROCESSORSUSER’S MANUALFirst EditionMotorola reserves the right to make change ..
MC68EC030FE40C , Second-Generation 32-Bit Enhanced Embedded Controller
MC14076B
4-Bit D-Type Register with Three-State Outputs
MC14076B
4-Bit D-Type Register
with Three-State Outputs
The MC14076B 4−Bit Register consists of four D−type flip−flops
operating synchronously from a common clock. OR gated
output−disable inputs force the outputs into a high−impedance state
for use in bus organized systems. OR gated data−disable inputs cause
the Q outputs to be fed back to the D inputs of the flip−flops. Thus they
are inhibited from changing state while the clocking process remains
undisturbed. An asynchronous master root is provided to clear all four
flip−flops simultaneously independent of the clock or disable inputs.
Features Three−State Outputs with Gated Control Lines Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing Asynchronous Master Reset Four Bus Buffer Registers Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
