MC14044BDR2 ,Quad R-S LatchesMAXIMUM RATINGS (Voltages Referenced to V )SSSymbol Parameter Value Unit16V DC Supply Voltage Range ..
MC14044BDR2G , CMOS MSI Quad R−S Latches
MC14044BDR2G , CMOS MSI Quad R−S Latches
MC14046B ,Phase Locked Loopsignals. The self−bias circuit adjusts small voltage signals in the linearregion of the amplifier. ..
MC14046BCL ,Phase Locked LoopMAXIMUM RATINGS* (Voltages Referenced to V )SSÎÎÎÎÎÎRating Symbol Value UnitÎÎÎÎÎÎ DC Supply Voltag ..
MC14046BCL ,Phase Locked LoopBLOCK DIAGRAMSELF BIAS PHASEPCA 14 2 PC1in outCIRCUIT COMPARATOR 1PHASE 13 PC2outPCB 3 COMPARATOR 2 ..
MC68376BGCAB20 , APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
MC6840CP ,Programmable timer module, 1 MHzMAXIMUM RATINGSThis devtce contains circuitry to protect theRatingSymbol Value UnitInputs agatnst d ..
MC6840CP ,Programmable timer module, 1 MHzMAXIMUM RATINGSThis devtce contains circuitry to protect theRatingSymbol Value UnitInputs agatnst d ..
MC6840P ,Programmable timer module, 1 MHzTHERMAL CHARACTERISTICS SVCC. Rellabllity of operation IS enhanced~,unused Inputs are tied to an ap ..
MC6845L ,CRT controller performs the interface to raster scan CRT displays
MC68488CP ,Speed: 1.0MHz; V(cc): -0.3 to +7.0V; V(in): -0.3 to +7.0V; ; general purpose interface adapter
MC14043B-MC14043BD-MC14043BFEL-MC14044B-MC14044BCP-MC14044BDR2
Quad R-S Latches
MC14043B, MC14044B
CMOS MSI
Quad R−S LatchesThe MC14043B and MC14044B quad R−S latches are constructed
with MOS P−Channel and N−Channel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three−state
buffers having a common enable input. The outputs are enabled with a
logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
Features Double Diode Input Protection Three−State Outputs with Common Enable Outputs Capable of Driving Two Low−power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature Range Supply Voltage Range = 3.0 Vdc to 18 Vdc Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
