MC14042BDR2 ,Quad Latchhttp://onsemi.cominput. Information present at the data input is transferred to outputs Qand Q duri ..
MC14043B ,Quad R-S LatchesMaximum ratings are those values beyond which device damage can occur.See detailed ordering and shi ..
MC14043BCL ,CMOS MSI Quad R-S LatchesMAXIMUM RATINGS* (Voltages Referenced to V )SSÎÎSymbol Parameter Value UnitThis device contains pro ..
MC14043BCL ,CMOS MSI Quad R-S Latches**SEMICONDUCTOR TECHNICAL DATA** Quad R–S LatchesThe MC14043B and MC14044B quad R–S latches are con ..
MC14043BCP ,CMOS MSI Quad R-S LatchesMAXIMUM RATINGS* (Voltages Referenced to V )SSÎÎSymbol Parameter Value UnitThis device contains pro ..
MC14043BD ,CMOS MSI Quad R-S LatchesMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
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MC68376BGCAB20 , APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
MC6840CP ,Programmable timer module, 1 MHzMAXIMUM RATINGSThis devtce contains circuitry to protect theRatingSymbol Value UnitInputs agatnst d ..
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MC14042B-MC14042BD-MC14042BDR2
Quad Latch
MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred
during the low clock level, and when the polarity input is in the logic
“1” state the transfer occurs during the high clock level.
Features Buffered Data Inputs Common Clock Clock Polarity Control Q and Q Outputs Double Diode Input Protection Supply Voltage Range = 3.0 Vdc to 1 8 Vdc Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
