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MC14035BCL-MC14035BCP
4-bit parallel-in/parallel-out shift register
--The MC14035B 4–bit shift register is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic structure.
It consists of a 4–stage clocked serial–shift register with synchronous
parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input
allows serial–right shifting of data or synchronous parallel loading via inputs
DP0 thru DP3. The True/Complement (T/C) input determines whether the
outputs display the Q or Q outputs of the flip–flop stages. J–K logic forms the
serial input to the first stage. With the J and K inputs connected together they
operate as a serial “D” input.
This device may be effectively used for shift–right/shift–left registers,
parallel–to–serial/serial–to–parallel conversion, sequence generation, up/
down Johnson or ring counters, pseudo–random code generation, frequen-
cy and phase comparators, sample and hold registers, etc... 4–Stage Clocked Serial–Shift Operation Synchronous Parallel Loading of all Four Stages J–K Serial Inputs on First Stage Asynchronous True/Complement Control of all Outputs Fully Static Operation Asynchronous Master Reset Data Transfer Occurs on the Positive–Going Clock Transition No Limit on Clock Rise and Fall Times All Inputs are Buffered Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
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ÎÎÎ Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
TRUTH TABLEX = Don’t Care
P/S = 0 = Serial Mode
T/C = 1 = True Outputs
SEMICONDUCTOR TECHNICAL DATA
