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MC14027B-MC14027BCP-MC14027BDR2-MC14027BFEL
Dual J-K Flip-Flop
MC14027B
Dual J-K Flip-Flop
The MC14027B dual J−K flip−flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip−flop. These devices may be
used in control, register, or toggle functions.
Features Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Swing Independent of Fanout Logic Edge−Clocked Flip−Flop Design Logic State is Retained Indefinitely with Clock Level Either High or
Low; Information is Transferred to the Output Only on the
Positive−Going Edge of the Clock Pulse Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range Pin−for−Pin Replacement for CD4027B Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
