MC14018BCL ,Presettable divide-by-N counterMAXIMUM RATINGS* (Voltages Referenced to V )ÎÎÎÎÎÎSSSymbol Parameter Value UnitÎÎFUNCTIONAL TRUTH T ..
MC14018BCL ,Presettable divide-by-N counterMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
MC14018BCP ,Presettable divide-by-N counterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ − 55CÎÎ 25CÎÎÎÎÎ 125CÎÎÎV VDDChar ..
MC14018BF ,Presettable Divdie-By-N CounterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎV VDD ..
MC14018BFEL ,Presettable Divdie-By-N Counter3MC14018B(7.)ÎÎÎÎÎ SWITCHING CHARACTERISTICS (C = 50 pF, T = 25* C)L AÎÎÎÎ All TypesÎÎÎV VDD DD(8. ..
MC14018BFR1 ,Presettable Divide-By-N CounterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎV VDD ..
MC6828L ,V(cc): -0.5 to +7.0V; priority interrupt controllerTHERMAL CHARACTERISTICSCharacteristic Symbol Ma; - - - jnitiThermal ReSISIance Cerdip RHJA 65 - -rc ..
MC6828P ,V(cc): -0.5 to +7.0V; priority interrupt controllerMAXIMUM RATINGSI Rating Symbol Value oi,"F (hoc?" Veltige " - - VCC - - l) 5107* 7 CL. - Vdci_ inpm ..
MC6828P ,V(cc): -0.5 to +7.0V; priority interrupt controllerBLOCK DIAGRAMLatched InputsW 11 o- 1-of-8[NS IO o--- Priority VectorDi? 9 th---- B-Bit Encoder Look ..
MC68302CFC16 ,Integrated Multiprotocol Processor User痵 ManualGeneral DescriptionSection 2 MC68000/MC68008 CoreSection 3 System Integration Block (SIB)Section 4 ..
MC68302FC16 ,Integrated Multiprotocol Processor User痵 ManualGeneral DescriptionSection 2 MC68000/MC68008 CoreSection 3 System Integration Block (SIB)Section 4 ..
MC68302FE16 ,Integrated multiprotocol processor (IMP). Frequency 16.67 MHz.Order this documentDEC 1 2 1990 by MC68302/DMOTOROLA_ TECHNICAL DATAF MC68302Integrated Multiprotoc ..
MC14018BCL
Presettable divide-by-N counter
-The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are synchronous,
and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input. Data on
the Jam inputs will then be transferred to their respective Q outputs
(inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic
1 state.
Division by any number from 2 to 10 can be accomplished by connecting
appropriate Q outputs to the data input, as shown in the Function Selection
table. Anti–lock gating is included in the MC14018B to assure proper
counting sequence. Fully Static Operation Schmitt Trigger on Clock Input Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range Pin–for–Pin Replacement for CD4018B
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ÎÎÎ Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
SEMICONDUCTOR TECHNICAL DATA
