MC14017BF ,Decade Counter3MC14017B(7.)ÎÎÎÎÎ SWITCHING CHARACTERISTICS (C = 50 pF, T = 25* C)L AÎ VÎDD(8.)Characteristic Sym ..
MC14017BFEL ,Decade Counter/Divider3MC14017BÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25C)L AÎÎÎÎÎÎ CharacteristicÎÎÎÎ ..
MC14017BFEL ,Decade Counter/Dividerpositive−going edge of the clock pulse. This part can be used infrequency division applications as ..
MC14017BFL2 ,Decade CounterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎV VDD ..
MC14018BCL ,Presettable divide-by-N counterMAXIMUM RATINGS* (Voltages Referenced to V )ÎÎÎÎÎÎSSSymbol Parameter Value UnitÎÎFUNCTIONAL TRUTH T ..
MC14018BCL ,Presettable divide-by-N counterMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
MC6828L ,V(cc): -0.5 to +7.0V; priority interrupt controllerTHERMAL CHARACTERISTICSCharacteristic Symbol Ma; - - - jnitiThermal ReSISIance Cerdip RHJA 65 - -rc ..
MC6828P ,V(cc): -0.5 to +7.0V; priority interrupt controllerMAXIMUM RATINGSI Rating Symbol Value oi,"F (hoc?" Veltige " - - VCC - - l) 5107* 7 CL. - Vdci_ inpm ..
MC6828P ,V(cc): -0.5 to +7.0V; priority interrupt controllerBLOCK DIAGRAMLatched InputsW 11 o- 1-of-8[NS IO o--- Priority VectorDi? 9 th---- B-Bit Encoder Look ..
MC68302CFC16 ,Integrated Multiprotocol Processor User痵 ManualGeneral DescriptionSection 2 MC68000/MC68008 CoreSection 3 System Integration Block (SIB)Section 4 ..
MC68302FC16 ,Integrated Multiprotocol Processor User痵 ManualGeneral DescriptionSection 2 MC68000/MC68008 CoreSection 3 System Integration Block (SIB)Section 4 ..
MC68302FE16 ,Integrated multiprotocol processor (IMP). Frequency 16.67 MHz.Order this documentDEC 1 2 1990 by MC68302/DMOTOROLA_ TECHNICAL DATAF MC68302Integrated Multiprotoc ..
MC14017-MC14017BF
Decade Counter
-The MC14017B is a five–stage Johnson decade counter with
built–in code converter. High speed operation and spike–free outputs
are obtained by use of a Johnson decade counter design. The ten
decoded outputs are normally low, and go high only at their
appropriate decimal time period. The output changes occur on the
positive–going edge of the clock pulse. This part can be used in
frequency division applications as well as decade counter or decimal
decode display applications. Fully Static Operation DC Clock Input Circuit Allows Slow Rise Times Carry Out Output for Cascading Divide–by–N Counting Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range Pin–for–Pin Replacement for CD4017B Triple Diode Protection on All Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Maximum Ratings are those values beyond which damage to the device
may occur. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
