MC14016BDR2 ,Quad Analog Switch / Quad MultiplexerMaximum ratings applied to the device are individual stress limit values (notnormal operating condi ..
MC14016BDR2 ,Quad Analog Switch / Quad MultiplexerELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎ − 55CÎ 25CÎÎÎÎ 125CÎÎÎV VDD DD(2) Vdc ..
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MC14016B-MC14016BD-MC14016BDR2-MC14016BFEL
Quad Analog Switch / Quad Multiplexer
MC14016B
Quad Analog Switch/
Quad Multiplexer
The MC14016B quad bilateral switch is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals. The
quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation.
Features Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical Pin−for−Pin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling
capacitance than CD4016) For Lower RON, Use The HC4016 High−Speed CMOS Device or
The MC14066B This Device Has Inputs and Outputs Which Do Not Have ESD
Protection. Antistatic Precautions Must Be Taken. Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.