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MC14014BCPG-MC14014BDR2G-MC14021BCPG-MC14021BDR2G Fast Delivery,Good Price
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MC14014BCPGONN/a4130avai8-Bit Static Shift Register
MC14014BDR2GMOTOROLAN/a49avai8-Bit Static Shift Register
MC14021BCPGONN/a270avai8-Bit Static Shift Register
MC14021BDR2GONN/a55000avai8-Bit Static Shift Register


MC14021BDR2G ,8-Bit Static Shift RegisterLOGIC DIAGRAMP1 P2 P3 P6 P7 P876 5 14 15 19P/S11D D QD QDQD QD QDSC C C C Q C Q C Q10CLOCKV = PIN 1 ..
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MC14014BCPG-MC14014BDR2G-MC14021BCPG-MC14021BDR2G
8-Bit Static Shift Register
MC14014B, MC14021B
8-Bit Static Shift Register
The MC14014B and MC14021B 8−bit static shift registers are
constructed with MOS P−channel and N−channel enhancement mode
devices in a single monolithic structure. These shift registers find primary
use in parallel−to−serial data conversion, synchronous and asynchronous
parallel input, serial output data queueing; and other general purpose
register applications requiring low power and/or high noise immunity.
Features
Synchronous Parallel Input/Serial Output (MC14014B) Asynchronous Parallel Input/Serial Output (MC14021B) Synchronous Serial Input/Serial Output Full Static Operation “Q” Outputs from Sixth, Seventh, and Eighth Stages Double Diode Input Protection Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range MC14014B Pin−for−Pin Replacement for CD4014B MC14021B Pin−for−Pin Replacement for CD4021B Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
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