MC14013BFL2 ,Dual D Flip-Flop3MC14013B(7.)ÎÎÎÎÎ SWITCHING CHARACTERISTICS (C = 50 pF, T = 25* C)L A(8.)Characteristic Symbol V ..
MC14014B ,8-Bit Static Shift RegisterMAXIMUM RATINGS (Voltages Referenced to V )SS1Symbol Parameter Value UnitV DC Supply Voltage Range ..
MC14014B ,8-Bit Static Shift RegisterMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
MC14014B ,8-Bit Static Shift RegisterMaximum ratings applied to the device are individual stress limit values (notnormal operating condi ..
MC14014B ,8-Bit Static Shift RegisterMAXIMUM RATINGS* (Voltages Referenced to V )SSÎÎÎÎÎÎT = – 55° to 125°C for all packages.ASymbol Par ..
MC14014B ,8-Bit Static Shift Register**SEMICONDUCTOR TECHNICAL DATA ** **The MC14014B and MC14021B 8–bit static shift registers are con ..
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MC68175 ,MC68175 FLEXchip Signal Processor Advance Information
MC14013BFL1-MC14013BFL2
Dual D Flip-Flop
---The MC14013B dual type D flip–flop is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each flip–flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flip–flops for counter and toggle applications. Static Operation Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Edge–Clocked Flip–Flop Design
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range Pin–for–Pin Replacement for CD4013B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Maximum Ratings are those values beyond which damage to the device
may occur. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
