MC14011BDTR2 ,Quad 2-Input NAND Gatehttp://onsemi.comThe B Series logic gates are constructed with P and N channelenhancement mode devi ..
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MC14011BFEL ,Quad 2-Input NAND GateMaximum ratings are those values beyond which device damage can occur.MC14001B Quad 2−Input NOR Gate
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MC6803CP ,1.0MHz; V(cc / in): -0.3 to +7.0V; 8-bit single-chip microcomputer (MCU)0 MOTOROLAM06801M06803SEMI CO N D U CTOR S35-01%;50 $LUESTE1NB§~VDW AUSTIN, TEXAS '73723' .MICROCOM ..
MC6803CP ,1.0MHz; V(cc / in): -0.3 to +7.0V; 8-bit single-chip microcomputer (MCU)0 MOTOROLAM06801M06803SEMI CO N D U CTOR S35-01%;50 $LUESTE1NB§~VDW AUSTIN, TEXAS '73723' .MICROCOM ..
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MC14001BDR2-MC14001BFEL-MC14011B-MC14011BDR2-MC14011BDTR2-MC14011BF-MC14011BFEL-MC14023B-MC14023BDR2-MC14023BFEL-MC14025BFEL-MC14071BFEL-MC14073BDR2-MC14073BFEL-MC14081BFEL
Quad 2-Input NOR Gate
MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082BThe B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features Supply Voltage Range = 3.0 Vdc to 18 Vdc All Outputs Buffered Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please