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MC10H351ML1
Quad TTL/NMOS to PECL* Translator
SEMICONDUCTOR TECHNICAL DATA --
The MC10H351 is a quad translator for interfacing data between a
saturated logic section and the PECL section of digital systems when only
a +5.0 Vdc power supply is available. The MC10H351 has TTL/NMOS
compatible inputs and PECL complementary open–emitter outputs that
allow use as an inverting/non–inverting translator or as a differential line
driver. When the common strobe input is at a low logic level, it forces all
true outputs to the PECL low logic state (≈ +3.2 V) and all inverting
outputs to the PECL high logic state (≈ +4.1 V).
The MC10H351 can also be used with the MC10H350 to transmit and
receive TTL/NMOS information differentially via balanced twisted pair
lines. Single +5.0 Power Supply All VCC Pins Isolated On Chip Differentially Drive Balanced Lines tpd = 1.3 nsec Typical
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (VCC = VCC1 = VCC2 = 5.0 V ± 5.0%)
DIP
PIN ASSIGNMENTB OUT
B OUT
N.C.
A OUT
A OUT
VCC
B IN
A IN
ECL VCC
C OUT
C OUT
D OUT
D OUT
VCC 2
C IN
N.C.
COMMON
STROBE
GND
D IN
TTL VCC
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
