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MC10H210MMOTON/a1950avai3-Input 3-Output OR Gate


MC10H210M ,3-Input 3-Output OR Gate2MC10H210PACKAGE DIMENSIONSPLCC–20FN SUFFIXPLASTIC PLCC PACKAGECASE 775–02ISSUE CM S S0.007 (0.180) ..
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MC10H210M
3-Input 3-Output OR Gate
---The MC10H210 is designed to drive up to six transmission lines
simultan– eously. The multiple outputs of this device also allow the
wire “OR”–ing of several levels of gating for minimization of gate and
package count.
The ability to control three parallel lines with minimum propagation
delay from a single point makes the MC10H210 particularly useful in
clock distribution applications where minimum clock skew is desired. Propagation Delay Average, 1.0 ns Typical Power Dissipation, 160 mW Typical Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT

VCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN11109765
VCC1 = PINS 1, 15
VCC2 = PIN 16
VEE = PIN 8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://
ORDERING INFORMATION
MARKING
DIAGRAMS
= Assembly Location = Wafer Lot = Year = Work Week
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775

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