MC10H172P ,Dual Binary 1-4-Decoder (High)
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MC10H172L-MC10H172P
Dual Binary to 1-4-Decoder(High)
SEMICONDUCTOR TECHNICAL DATA! -
The MC10H172 is a binary coded 2 line to dual 4 line decoder with
selected outputs high. With either E0 or E1 low, the corresponding
selected 4 outputs are low. The common enable E, when high, forces all
outputs low. Propagation Delay, 2 ns Typical Power Dissipation 325 mW Typical (same as MECL 10K) Improved Noise Margin 150 mV (over operating voltage and
temperature range) Voltage Compensated MECL 10K–Compatible
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
AC PARAMETERS
NOTE:Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated
through a 50–ohm resistor to –2.0 volts.
DIP
PIN ASSIGNMENTVCC1
Q13
Q12
Q11
Q10
VEE
VCC2
Q00
Q01
Q02
Q03
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
