MC10H117D ,Dual 2-Wide 2-3-Input OR-AND/NOT (OR-AND) Gate2MC10H117PACKAGE DIMENSIONSPLCC–20FN SUFFIXPLASTIC PLCC PACKAGECASE 775–02ISSUE CM S S0.007 (0.180) ..
MC10H117FN ,Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate**SEMICONDUCTOR TECHNICAL DATA* *The MC10H117 dual 2–wide 2–3–input OR–AND/OR–AND–Invert gate is ..
MC10H117FN ,Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
MC10H117FNR2 ,Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
MC10H117FNR2 ,Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gatefeatures of an ECL device make itrequirement stems only from the speed performance aspectideal for ..
MC10H117L ,Dual 2-Wide 2-3-input OR-AND/OR-AND GateMAXIMUM RATINGSCharacteristic Symbol Rating Unit45Power Supply (V = 0) V –8.0 to 0 VdcCC EE3Input V ..
MC34164D-3 ,Micropower Undervoltage Sensing CircuitMAXIMUM RATINGSRating Symbol Value UnitPower Input Supply Voltage V –1.0 to 12 VinReset Output Volt ..
MC34164D-3R2 ,MicroPower UnderVoltage Sensing Circuit3V , OUTPUT VOLTAGE (V)OV , OUTPUT VOLTAGE (V)OMC34164, MC33164, NCV331645.0 5.04.0 4.03.0 3.02.0 ..
MC34164D-5 ,Micropower Undervoltage Sensing CircuitMAXIMUM RATINGSRating Symbol Value UnitPower Input Supply Voltage V –1.0 to 12 VinReset Output Volt ..
MC34164P-003 ,MicroPower UnderVoltage Sensing CircuitMAXIMUM RATINGSRating Symbol Value UnitPower Input Supply Voltage V −1.0 to 12 VinReset Output Volt ..
MC34164P-005 ,MicroPower UnderVoltage Sensing Circuit3V , OUTPUT VOLTAGE (V)OV , OUTPUT VOLTAGE (V)OMC34164, MC33164, NCV331645.0 5.04.0 4.03.0 3.02.0 ..
MC34164P-3 ,MICROPOWER UNDERVOLTAGE SENSING CIRCUITSELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T is the operating ambi ..
MC10H117D
Dual 2-Wide 2-3-Input OR-AND/NOT (OR-AND) Gate
-- -The MC10H11 7 dual 2–wide 2–3–input OR–AND/
OR–AND–Invert gate is a general purpose logic element designed for
use in data control, such as digital multiplexing or data distribution.
Pin 9 is common to both gates. This MECL 10H part is a
functional/pinout duplication of the standard MECL 10K family part,
with 100% improvement in propagation delay, and no increase in
power–supply current. Propagation Delay, 1.0 ns Typical Power Dissipation 100 mW/Gate Typical (same as MECL 10K) Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
LOGIC DIAGRAM
DIP
PIN ASSIGNMENTVCC1
AOUT
AOUT
A1IN
A1IN
A2IN
A2IN
VEE
VCC2
BOUT
BOUT
B1IN
B1IN
B2IN
B2IN
A2IN, B2IN
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://
ORDERING INFORMATION
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
