MC10H106FN ,Triple 4-3-3 Input NOR GateELECTRICAL CHARACTERISTICS (V = –5.2 V ±5%) (See Note 1.)EE0° 25° 75°Symbol Characteristic Min Max ..
MC10H106FN ,Triple 4-3-3 Input NOR Gate**SEMICONDUCTOR TECHNICAL DATA** * ** The MC10H106 is a triple 4–3–3 input NOR gate. This 10H part ..
MC10H106FNR2 ,Triple 4-3-3-Input NOR Gate3Differential ECLAN1406/DThe traditional choice of a negative power supply for ECL for both the 10H ..
MC10H106FNR2 ,Triple 4-3-3-Input NOR GateLOGIC DIAGRAM14165PDIP–163MC10H106P6P SUFFIX7AWLYYWWCASE 6481910 2 111PLCC–2010H10612FN SUFFIXAWLYY ..
MC10H106L ,Triple 4-3-3-Onput NOR GateMAXIMUM RATINGSPLCCCharacteristic Symbol Rating UnitCASE 775–02Power Supply (V = 0) V –8.0 to 0 Vdc ..
MC10H106M ,Triple 4-3-3-Input NOR Gate3AN1672/DSection 2: Translation from Different ECL Operating Mode Drivers to Non ECL ReceiversThe f ..
MC34118DW ,VOICE SWITCHED SPEAKERPHONE CIRCUITfeatures of a featurephone.0 Improved Attenuator Gain Range: 52 dB Between Transmitand Receive. Low ..
MC34118P ,VOICE SWITCHED SPEAKERPHONE CIRCUITfeatures of a featurephone.0 Improved Attenuator Gain Range: 52 dB Between Transmitand Receive. Low ..
MC34118P. ,VOICE SWITCHED SPEAKERPHONE CIRCUITfeatures of a featurephone.0 Improved Attenuator Gain Range: 52 dB Between Transmitand Receive. Low ..
MC34119D ,LOW POWER AUDIO AMPLIFIEROrder this document by MC34119/D* ** ** The MC34119 is a low power audio amplifier intergrated circ ..
MC34119DTB ,LOW POWER AUDIO AMPLIFIERELECTRICAL CHARACTERISTICS (T = 25°C, unless otherwise noted.)ACharacteristics Symbol Min Typ Max U ..
MC34119DTBR2 , LOW POWER AUDIO AMPLIFIER
MC10H106FN-MC10H106FNR2-MC10H106MEL
Triple 4-3-3-Input NOR Gate
--The MC10H106 is a triple 4–3–3 input NOR gate. This 10H part is a
functional/pinout duplication of the standard MECL 10K family part,
with 100% improvement in propagation delay and no increase in
power– supply current. Propagation Delay, 1.0 ns Typical Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
LOGIC DIAGRAM
DIP
PIN ASSIGNMENTVCC1
BOUT
AOUT
AIN
AIN
AIN
AIN
VEE
VCC2
COUT
CIN
CIN
CIN
BIN
BIN
BIN
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8 15 2 36
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://
ORDERING INFORMATION
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
CDIP–16
L SUFFIX
CASE 620A
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
