MC10H104FNR2 ,Quad 2-Input AND GateMAXIMUM RATINGSSymbol Characteristic Rating UnitV Power Supply (V = 0) –8.0 to 0 VdcEE CCV Input Vo ..
MC10H104L ,Quad 2-Input AND GateLOGIC DIAGRAM— Surge 100Operating Temperature Range T 0 to +75 °C 4A25Storage Temperature Range — P ..
MC10H104M ,Quad 2-Input AND GateLOGIC DIAGRAM1642 PDIP–16MC10H104P5P SUFFIXAWLYYWWCASE 64863171101411PLCC–2010H10412 FN SUFFIX9AWLY ..
MC10H104MEL ,Quad 2-Input AND GatePrepared by: Paul ShockmanON SemiconductorAPPLICATION NOTEObjectiveGeneral BackgroundThis applicati ..
MC10H104ML1 ,Quad 2-Input AND Gate**SEMICONDUCTOR TECHNICAL DATA* * The MC10H104 is a quad 2–input AND gate. One of the gates has bo ..
MC10H104ML1 ,Quad 2-Input AND GateMAXIMUM RATINGSPLCCCASE 775–02Characteristic Symbol Rating UnitPower Supply (V = 0) V –8.0 to 0 Vdc ..
MC34081BP ,High Slew Rate, High Bandwidth, JFET Input Operational AmplifierELECTRICAL CHARACTERISTICS (V = +15 V, V = – 15 V, T = T to T [Note 3], unless otherwise noted.)CC ..
MC34081P ,HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERSfeatures largeoutput voltage swing, no deadband crossover distortion, high capacitivedrive capabili ..
MC34081P ,HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERSMAXIMUM RATINGSRating Symbol Value UnitSupply Voltage (from V to V ) V +44 VCC EE SInput Differenti ..
MC34082AP , HIGH SLEW RATE, WIDE BANDWIDTH, JEFT INPUT OPERATIONAL AMPLIFIERS
MC34082AP , HIGH SLEW RATE, WIDE BANDWIDTH, JEFT INPUT OPERATIONAL AMPLIFIERS
MC34082P ,HIGH PERFORMANCE JFET INPUT OPERATIONAL AMPLIFIERSOrder this document by MC34080/Dt*$*"%* & **$** &**$** * **!%$*!*"*$* **!**"#HIGH PERFORMANCEThese ..
MC10H104FNR2-MC10H104M
Quad 2-Input AND Gate
---The MC10H104 is a quad 2–input AND gate. One of the gates has
both AND/NAND outputs available. This MECL 10H part is a
functional/pinout duplication of the standard MECL 10K family part,
with 100% improvement in propagation delay, and no increase in
power– supply current. Propagation Delay, 1.0 ns Typical Power Dissipation 25 mW/Gate (same as MECL 10K) Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
LOGIC DIAGRAM
DIP
PIN ASSIGNMENTVCC1
AOUT
BOUT
AIN
AIN
BIN
BIN
VEE
VCC2
DOUT
COUT
DIN
DIN
CIN
CIN
DOUT
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 875
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://
ORDERING INFORMATION
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
