MC10H016 ,4-Bit Binary CounterLogic DiagramPEQ0 Q1 Q2 Q3MASTER SLAVE MASTER SLAVE MASTER SLAVEQ Q QP1 P2 P3P0Q Q QQ Q QQMRCECPTCN ..
MC10H016FNR2 ,4-Bit Binary CounterPrepared by: Paul ShockmanON SemiconductorAPPLICATION NOTEObjectiveGeneral BackgroundThis applicati ..
MC10H016FNR2 ,4-Bit Binary Counter3Differential ECLAN1406/DThe traditional choice of a negative power supply for ECL for both the 10H ..
MC10H016L ,4-Bit Binary CounterELECTRICAL CHARACTERISTICS (V = –5.2 V ±5%) (See Note)EE0° 25° 75°V V1 16CC1 CC2Characteristic Symb ..
MC10H100 ,Quad 2-Input NOR Gate With Strobe3Differential ECLAN1406/DThe traditional choice of a negative power supply for ECL for both the 10H ..
MC10H100L ,Quad 2**SEMICONDUCTOR TECHNICAL DATA* * ** **The MC10H100 is a quad NOR gate. Each gate has 3 inputs, tw ..
MC34064SN-5T1G , Undervoltage Sensing Circuit
MC34065P ,HIGH PERFORMANCE DUAL CHANNEL CURRENT MODE CONTROLLEROrder this document by MC34065/D * *HIGH PERFORMANCE* *DUAL CHANNEL CURRENTThe MC34065 is a high p ..
MC34065P-H ,HIGH PERFORMANCE DUAL CHANNEL CURRENT MODE CONTROLLERSOrder this document by MC34065–H/D* ** ** * ** **HIGH PERFORMANCEThe MC34065–H,L series are high p ..
MC34065P-H ,HIGH PERFORMANCE DUAL CHANNEL CURRENT MODE CONTROLLERSELECTRICAL CHARACTERISTICS (V = 15 V [Note 2], R = 8.2 kΩ, C = 3.3 nF, for typical values T = 25°C, ..
MC34065P-L ,HIGH PERFORMANCE DUAL CHANNEL CURRENT MODE CONTROLLERSfeatures consisting of input and referenceundervoltage lockouts each with hysteresis, cycle–by–cycl ..
MC34066P ,HIGH PERFORMANCE RESONANT MODE CONTROLLERSfeatures consisting of a high speed faultcomparator and latch, programmable soft–start circuitry, i ..
MC10H016
4-Bit Binary Counter
--The MC10H016 is a high–speed synchronous, presettable,
cascadable 4–bit binary counter. It is useful for a large number of
conversion, counting and digital integration applications. Counting Frequency, 200 MHz Minimum Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible Positive Edge Triggered
DIP
PIN ASSIGNMENTVCC1
VEE
VCC2
TRUTH TABLEZ = Clock Pulse (Low to High);ZZ = Clock Pulse (High to Low)
Features include assertion inputs and outputs on each
of the four master/slave counting flip–flops. Terminal
count is generated internally in a manner that allows
synchronous loading at nearly the speed of the basic
counter.
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://
ORDERING INFORMATION
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
