MC10EP32DG ,3.3V 5V ECL / 2 Divider3MC10EP32, MC100EP32Table 6. 10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)CC EE−40°C 25 ..
MC10EP32DR2 ,3.3V / 5V ECL ÷2 DividerAN1672/DThe ECL Translator GuidePECL • LVPECL • NECL • TTL •LVTTL/LVCMOS • CMOS
MC10EP32DT ,3.3V / 5V ECL ÷2 Divider3MC10EP32, MC100EP32Table 6. 10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)CC EE−40°C 25 ..
MC10EP32DTG , 3.3V / 5V ECL ÷2 Divider
MC10EP33D ,3.3V / 5V ECL Divide By 4 Divider2AND8009/Dreference voltages (VSPICE Netlists , V , V , etc.) should be drivenBB CS HSTLThe netlist ..
MC10EP33DG , 3.3V / 5V ECL ÷4 Divider
MC34063EB ,DC-DC CONVERTER CONTROL CIRCUITSMC34063AMC34063EDC/DC CONVERTER CONTROL CIRCUITS
MC10EP32DG
3.3V 5V ECL / 2 Divider
MC10EP32, MC100EP32
3.3V / 5V�ECL �2 Divider
The MC10/100EP32 is an integrated �2 divider with differential
CLK inputs.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 �F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power−up, the internal flip−flops will attain a random state; the
reset allows for the synchronization of multiple EP32’s in a system.
The 100 Series contains temperature compensation. 350 ps Typical Propagation Delay Maximum Frequency > 4 GHz Typical (Figure 3) PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs Q Output Will Default LOW with Inputs Open or at VEE Pb−Free Package is Available
