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MC10EP016FAR2
3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
MC10EP016, MC100EP016
3.3V / 5V�ECL 8-Bit
Synchronous Binary
Up Counter
The MC10/100EP016 is a high–speed synchronous, presettable,
cascadeable 8–bit binary counter. Architecture and operation are the
same as the MC10E016 in the ECLinPS family.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an all–one state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
non–cascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation. 500 ps Typical Propagation Delay PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V
with VEE = –3.0 V to –5.5 V Open Input Default State Safety Clamp on Inputs Internal TC Feedback (Gated) Addition of COUT and COUT 8–Bit Differential Clock Input VBB Output Fully Synchronous Counting and TC Generation Asynchronous Master Reset
