MC10211P ,Dual 3-Input/3-Output NOR GateLOGIC DIAGRAM235DIP467PIN ASSIGNMENT12139V V1 16CC1 CC210 1411A V2 15OUT CC1BV = PIN 1, 15 A 3 14OU ..
MC10212L ,High Speed Dual 3-Input/3-Output OR/NOR GateLOGIC DIAGRAM43DIP562PIN ASSIGNMENT71213 V V1 16CC1 CC29101411VA 2 15CC1OUTA B3 14OUT OUTA BV = PIN ..
MC10212P ,High Speed Dual 3-Input/3-Output OR/NOR GateLOGIC DIAGRAM43DIP562PIN ASSIGNMENT71213 V V1 16CC1 CC29101411VA 2 15CC1OUTA B3 14OUT OUTA BV = PIN ..
MC10212P ,High Speed Dual 3-Input/3-Output OR/NOR GateELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10216 ,High Speed Triple Line ReceiverELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10216FN ,High Speed Triple Line ReceiverLOGIC DIAGRAMA C2 15OUT OUT4 2A 3 14 COUT OUT5 3A C4 13IN IN9 6A C5 12IN IN10 7VB 6 11OUT BB12 14B ..
MC3374FTB ,LOW VOLTAGE SINGLE CONVERSION FM RECEIVEROrder this document by MC3374/D * ** * **. . . with single conversion circuitry including oscillat ..
MC33761SNT1-025 ,Ultra Low-Noise Low Dropout Voltage Regulator with 1.0 V ON/OFF Control3MC33761DEFINITIONSLoad Regulation Line RegulationThe change in output voltage for a change in outp ..
MC33761SNT1-025 ,Ultra Low-Noise Low Dropout Voltage Regulator with 1.0 V ON/OFF ControlFeaturesMARKING DIAGRAM• Ultra−Low Noise: 150 nV/√Hz @ 100 Hz, 40 VRMS100 Hz−100 kHz Typical, I = ..
MC33761SNT1-025 ,Ultra Low-Noise Low Dropout Voltage Regulator with 1.0 V ON/OFF ControlELECTRICAL CHARACTERISTICS(For typical values T = 25°C, for min/max values T = −40°C to +85°C, max ..
MC33761SNT1-029 ,Ultra Low-Noise Low Dropout Voltage Regulator with 1.0 V ON/OFF ControlELECTRICAL CHARACTERISTICS (continued)(For typical values T = 25°C, for min/max values T = −40°C to ..
MC33761SNT1-50 , Ultra Low-Noise Low Dropout Voltage Regulator with 1V ON/OFF Control
MC10211L-MC10211P
Dual 3-Input/3-Output NOR Gate
SEMICONDUCTOR TECHNICAL DATA -
The MC10211 is designed to drive up to six transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR”–ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines with minimum propagation delay
from a single point makes the MC10211 particularly useful in clock distribution
applications where minimum clock skew is desired. = 160 mW typ/pkg (No Loads)
tpd = 1.5 ns typ (All Output Loaded)
tr, tf = 1.5 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1, 15
VCC2 = PIN 16
VEE = PIN 8109 1365 3
DIP
PIN ASSIGNMENTVCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
