MC10210L ,Dual 3-Input/3-Output OR GateLOGIC DIAGRAM56 2DIP73PIN ASSIGNMENT4910 12 V V1 16CC1 CC21113VA 2 15CC1OUT14A 3 14 BOUT OUTV = PIN ..
MC10210P ,Dual 3-Input/3-Output OR GateLOGIC DIAGRAM56 2DIP73PIN ASSIGNMENT4910 12 V V1 16CC1 CC21113VA 2 15CC1OUT14A 3 14 BOUT OUTV = PIN ..
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MC10211L ,Dual 3-Input/3-Output NOR GateLOGIC DIAGRAM235DIP467PIN ASSIGNMENT12139V V1 16CC1 CC210 1411A V2 15OUT CC1BV = PIN 1, 15 A 3 14OU ..
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MC3372P ,LOW POWER FM IFBlock Diagram and Test Fixture SchematicRSSI OutputRF InputV = 4.0 VdcFilterCCIn1.0 μF0.1Filter51 k ..
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MC3374FTB ,LOW VOLTAGE SINGLE CONVERSION FM RECEIVEROrder this document by MC3374/D * ** * **. . . with single conversion circuitry including oscillat ..
MC10210L-MC10210P
Dual 3-Input/3-Output OR Gate
SEMICONDUCTOR TECHNICAL DATA -
The MC10210 is designed to drive up to six transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR” –ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines with minimum propagation delay
from a single point makes the MC10210 particularly useful in clock distribution
applications where minimum clock skew is desired. = 160 mW typ/pkg (No Loads)
tpd = 1.5 ns typ (All Output Loaded)
tr, tf = 1.5 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1, 15
VCC2 = PIN 16
VEE = PIN 8111095
DIP
PIN ASSIGNMENTVCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
