MC10186L ,Hex D Master-Slave Flip-Flop With ResetLOGIC DIAGRAMDIPPIN ASSIGNMENTD0 5 2 Q0RESET 1 16 VCCQ0 2 15 Q5D1 6 3 Q1 Q1 Q43 14Q2 Q34 13D5D0 5 1 ..
MC10186P ,Hex D Master-Slave Flip-Flop With ResetLOGIC DIAGRAMDIPPIN ASSIGNMENTD0 5 2 Q0RESET 1 16 VCCQ0 2 15 Q5D1 6 3 Q1 Q1 Q43 14Q2 Q34 13D5D0 5 1 ..
MC10188FN ,Hex Buffer With EnableELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10188FNR2 ,Hex Buffer With EnableELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10188FNR2 ,Hex Buffer With Enable**SEMICONDUCTOR TECHNICAL DATA * *The MC10188 is a high–speed hex buffer with a common Enable inp ..
MC10188FNR2 ,Hex Buffer With EnableLOGIC DIAGRAMFN SUFFIXPLCCXOUT9 CASE 775–022Y536DIP47PIN ASSIGNMENT1310V 1 16 VCC1 CC22 15 FA14 OUT ..
MC3361CD ,LOW POWER NARROWBAND FM IFMAXIMUM RATINGS (T A = 25°C, unless otherwise noted.)Rating Pln Symbol Value UnitPower Supply Volta ..
MC3361CDR2 ,V(dc): 10V; ; low power narrowband FM IFOrder this document by MC3361C/D**The MC3361C includes an Oscillator, Mixer, Limiting Amplifier,Qua ..
MC3361CP ,LOW POWER NARROWBAND FM IFMAXIMUM RATINGS (T A = 25°C, unless otherwise noted.)Rating Pln Symbol Value UnitPower Supply Volta ..
MC3361N , LOW POWER NARROW BAND FM IF
MC3362 ,LOW-POWER DUAL CONVERSION FM RECEIVEROrder this document by MC3362/D **. . . includes dual FM conversion with oscillators, mixers, quad ..
MC3362DW ,LOW-POWER DUAL CONVERSION FM RECEIVEROrder this document by MC3362/D **. . . includes dual FM conversion with oscillators, mixers, quad ..
MC10186FN-MC10186L-MC10186P
Hex D Master-Slave Flip-Flop With Reset
LOGIC DIAGRAMVCC = PIN 16
VEE = PIN 8 5
CLOCK
RESET1
Q0
3 Q1
4 Q2 Q3 Q4 Q5
SEMICONDUCTOR TECHNICAL DATA --
The MC10186 contains six high–speed, master slave type “D” flip–flops.
Clocking is common to all six flip–flops. Data is entered into the master when
the clock is low. Master to slave data transfer takes place on the positive–going
Clock transition. Thus, outputs may change only on a positive–going Clock
transition. A change in the information present at the data (D) input will not affect
the output information any other time due to the master–slave construction of
this device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT. RESET = 460 mW typ/pkg (No Load)
ftoggle= 150 MHz (typ)
tr, tf = 2.0 ns typ (20%–80%)
CLOCKED TRUTH TABLE*A clock H is a clock transition
from a low to a high state.
DIP
PIN ASSIGNMENTRESET
VEE
VCC
CLOCK
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
