MC10173L ,Quad 2-Input Multiplexer/ LatchLOGIC DIAGRAMSELECT 9DIP1 Q0PIN ASSIGNMENTD00 6Q0 VD01 5 1 16CCQ1 Q22 152 Q1D11 3 14 Q3D10 4D1 ..
MC10173P ,Quad 2-Input Multiplexer/LatchLOGIC DIAGRAMSELECT 9DIP1 Q0PIN ASSIGNMENTD00 6Q0 VD01 5 1 16CCQ1 Q22 152 Q1D11 3 14 Q3D10 4D1 ..
MC10174FN ,Dual 4 to 1 MultiplexerELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10174FN ,Dual 4 to 1 MultiplexerELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10174FN ,Dual 4 to 1 MultiplexerELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10174FNR2 ,Dual 4 to 1 Multiplexer**SEMICONDUCTOR TECHNICAL DATA* * ** * The MC10174 is a high speed dual channel multiplexer with ou ..
MC3358P1 ,Dual, Low Power Operational AmplifierOrder this document by MC3458/D** ** ** *DUAL DIFFERENTIALUtilizing the circuit designs perfected ..
MC3359 ,HIGH GAIN LOW POWER FM IFOrder this document by MC3359/D ** * ** **...includes oscillator, mixer, limiting amplifier, AFC, ..
MC33591 ,MC33591 PLL Tuned UHF Receiver for Data Transfer Applicationsblock diagramTable 1: Ordering InformationRF frequency/ AmbiantDevice PackageIF filter bandwidth Te ..
MC33591FTA ,PLL Tuned UHF Receiver for Data Transfer ApplicationsFEATURES• 315MHz, 434MHz BandsPin Connections• OOK and FSK Demodulation• Low Current Consumption: 5 ..
MC33592FTA ,PLL Tuned UHF Receiver for Data Transfer ApplicationsMAXIMUM RATINGSParameter Symbol Value UnitV CCV - 0.3 to 5.5Supply Voltage VGND VCCLNAV - 0.3GND Vo ..
MC33594FTA ,PLL Tuned UHF Receiver for Data Transfer ApplicationsMAXIMUM RATINGSParameter Symbol Value UnitV CCV - 0.3 to 5.5Supply Voltage VGND VCCLNAV - 0.3GND Vo ..
MC10173L-MC10173P
Quad 2-Input Multiplexer/ Latch
SEMICONDUCTOR TECHNICAL DATA -
The MC10173 is a quad two channel multiplexer with latch. It incorporates
common clock and common data select inputs. The select input determines
which data input is enabled. A high (H) level enables data inputs D00, D10,
D20, and D30 and a low (L) level enables data inputs D01, D11, D21, D31. Any
change on the data input will be reflected at the outputs while the clock is low.
The outputs are latched on the positive transition of the clock. While the clock is
in the high state, a change in the information present at the data inputs will not
affect the output information. = 275 mW typ/pkg (No Load)
tpd = 2.5 ns typ
tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAMVCC = PIN 16
VEE = PIN 8
1 Q0
2 Q1
15 Q2
14 Q3
SELECT 9
D00 6
D01 5
D10 4
D11 3
D20 13
D21 12
D30 11
D31 10
CLOCK 7
TRUTH TABLE
DIP
PIN ASSIGNMENTD11
D10
D01
D00
CLOCK
VEE
VCC
D20
D21
D30
D31
SELECT
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
