MC10172L ,Dual Binary to 1-4 Decoder(High)LOGIC DIAGRAMCASE 648–08FN SUFFIXE0 14PLCC10 Q0 3CASE 775–0211 Q0 212 Q0 1DIPA 9PIN ASSIGNMENT13 Q0 ..
MC10172P ,Dual Binary to 1-4 Decoder(High)LOGIC DIAGRAMCASE 648–08FN SUFFIXE0 14PLCC10 Q0 3CASE 775–0211 Q0 212 Q0 1DIPA 9PIN ASSIGNMENT13 Q0 ..
MC10173 ,Quad 2-Input Multiplexer/LatchELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10173L ,Quad 2-Input Multiplexer/ LatchLOGIC DIAGRAMSELECT 9DIP1 Q0PIN ASSIGNMENTD00 6Q0 VD01 5 1 16CCQ1 Q22 152 Q1D11 3 14 Q3D10 4D1 ..
MC10173P ,Quad 2-Input Multiplexer/LatchLOGIC DIAGRAMSELECT 9DIP1 Q0PIN ASSIGNMENTD00 6Q0 VD01 5 1 16CCQ1 Q22 152 Q1D11 3 14 Q3D10 4D1 ..
MC10174FN ,Dual 4 to 1 MultiplexerELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC3356P ,GENERAL PURPOSE TRANSISTOR ARRAYOrder this document by MC3346/D* * ** * **GENERAL PURPOSE** * TRANSISTOR ARRAYThe MC3346 is des ..
MC3357D ,LOW POWER FM IFMAXIMUM RATINGS (T = 25°C, unless otherwise noted)ARating Pin Symbol Value UnitPower Supply Voltage ..
MC3357P ,LOW POWER FM IFOrder this document by MC3357/D ** * ** **. . . includes Oscillator, Mixer, Limiting Amplifier, Qu ..
MC3358P1 ,Dual, Low Power Operational AmplifierOrder this document by MC3458/D** ** ** *DUAL DIFFERENTIALUtilizing the circuit designs perfected ..
MC3359 ,HIGH GAIN LOW POWER FM IFOrder this document by MC3359/D ** * ** **...includes oscillator, mixer, limiting amplifier, AFC, ..
MC33591 ,MC33591 PLL Tuned UHF Receiver for Data Transfer Applicationsblock diagramTable 1: Ordering InformationRF frequency/ AmbiantDevice PackageIF filter bandwidth Te ..
MC10172L-MC10172P
Dual Binary to 1-4 Decoder(High)
SEMICONDUCTOR TECHNICAL DATA! -
The MC10172 is a binary-coded 2 line to dual 4 line decoder with selected
outputs high. With either E0 or E1 low, the corresponding selected 4 outputs are
low. The common enable E, when high, forces all outputs low. = 325 mW typ/pkg (No Load)
tpd = 4.0 ns typ
tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
E0 14
A 9
B 7
E 15
E1 2
10 Q0 3
11 Q0 2
12 Q0 1
13 Q0 0
3 Q1 3
4 Q1 2
5 Q1 1
6 Q1 0
TRUTH TABLE
DIP
PIN ASSIGNMENTVCC1
Q13
Q12
Q11
Q10
VEE
VCC2
Q00
Q01
Q02
Q03
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).