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MC10162L-MC10162P
Binary to 1-8 Decoder(High)
SEMICONDUCTOR TECHNICAL DATA -
The MC10162 is designed to convert three lines of input data to a
one–of–eight output. The selected output will be high while all other outputs are
low. The enable inputs, when either or both are high, force all outputs low.
The MC10162 is a true parallel decoder. No series gating is used internally,
eliminating unequal delay times found in other decoders.
This device is ideally suited for demultiplexer applications. One of the two
enable inputs is used as the data input, while the other is used as a data enable
input.
A complete mux/demux operation on 16 bits for data distribution is illustrated
in Figure 1 of the MC10161 data sheet. = 315 ns typ/pkg (No Load)
tpd = 4.0 ns typ
tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
E02
E115
C14
6Q0
5Q1
4Q2
3Q3Q4Q5Q6Q7
TRUTH TABLE
DIP
PIN ASSIGNMENTVCC1
VEE
VCC2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
