MC10161P ,Binary to 1-8 Decoder (Low)**SEMICONDUCTOR TECHNICAL DATA ** * The MC10161 is designed to decode a three bit input word to a ..
MC10161P ,Binary to 1-8 Decoder (Low)LOGIC DIAGRAMPIN ASSIGNMENTE0 2V = PIN 1CC1E1 15V = PIN 16 CC26Q0V = PIN 8EE V 1 16 VCC1 CC25Q1E0 2 ..
MC10162L ,Binary to 1-8 Decoder(High)LOGIC DIAGRAME02E115DIP6Q0PIN ASSIGNMENT5Q1V 1 16 VCC1 CC24Q2A7E0 2 15 E13Q33 14 CQ313 Q4B9 Q2 4 13 ..
MC10162P ,Binary to 1-8 Decoder(High)LOGIC DIAGRAME02E115DIP6Q0PIN ASSIGNMENT5Q1V 1 16 VCC1 CC24Q2A7E0 2 15 E13Q33 14 CQ313 Q4B9 Q2 4 13 ..
MC10164FNR2 ,8-Line MultiplexerELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10164L ,8-Line MultiplexerLOGIC DIAGRAMCASE 648–08FN SUFFIXPLCCA 7CASE 775–02B 9C 10DIPEnable 215 ZPIN ASSIGNMENTX0 ..
MC3346P ,General purpose transistor arrayOrder this document by MC3346/D* * ** * **GENERAL PURPOSE** * TRANSISTOR ARRAYThe MC3346 is des ..
MC33470DW ,SYNCHRONOUS RECTIFICATION DC/DC CONVERTER PROGRAMMABLE INTEGRATED CONTROLLERThermal CharacteristicsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁMaximum Power DissipationÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ..
MC33470DWR2 ,Synchronous Rectification, DC/DC Converter, Programmable Integrated ControllerThermal CharacteristicsMaximum Power DissipationÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ..
MC33493DTB ,PLL tuned UHF Transmitter for Data Transfer ApplicationsFEATURES• Selectable frequency bands:DATACLK 1 MODE 14315-434MHz and 868-928MHz• OOK and FSK modula ..
MC33493DTB ,PLL tuned UHF Transmitter for Data Transfer Applicationsblock diagramThis document contains information on a new product under development. Motorola Motor ..
MC33502D ,1V, Rail-to-Rail, Dual Operational Amplifier
MC10161FNR2-MC10161P
Binary to 1-8 Decoder (Low)
SEMICONDUCTOR TECHNICAL DATA -
The MC10161 is designed to decode a three bit input word to a one of eight
line output. The selected output will be low while all other outputs will be high. The
enable inputs, when either or both are high, force all outputs high.
The MC10161 is a true parallel decoder. No series gating is used internally,
eliminating unequal delay times found in other decoders. This design provides
the identical 4 ns delay from any address or enable input to any output.
A complete mux/demux operation on 16 bits for data distribution is illustrated
in Figure 1. This system, using the MC10136 control counters, has the
capability of incrementing, decrementing or holding data channels. When both
S0 and S1 are low, the index counters reset, thus initializing both the mux and
demux units. The four binary outputs of the counter are buffered by the
MC10101s to send twisted–pair select data to the multiplexer/demultiplexer to
units. = 315 mW typ/pkg (No Load)
tpd = 4.0 ns typ
tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8215
C14
6Q0
5Q1
4Q2
3Q3Q4Q5Q6Q7
TRUTH TABLE
DIP
PIN ASSIGNMENTVCC1
VEE
VCC2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
