MC10141L ,Four Bit Universal Shift RegisterLOGIC DIAGRAMD3 D2 D1 D0DIPParallel EnterS1PIN ASSIGNMENT 1 of 4 DecoderS2Shift RightV V1 16CC1 CC2 ..
MC10141L. ,Four Bit Universal Shift Register**SEMICONDUCTOR TECHNICAL DATA * **The MC10141 is a four–bit universal shift register which perfo ..
MC10141P ,Four Bit Universal Shift RegisterLOGIC DIAGRAMD3 D2 D1 D0DIPParallel EnterS1PIN ASSIGNMENT 1 of 4 DecoderS2Shift RightV V1 16CC1 CC2 ..
MC10153L ,Quad LatchLOGIC DIAGRAMD0 3Q02Q0G0 5DIP6Q1D1 7Q1 PIN ASSIGNMENTCE 4V V1 16CC1 CC2C 13CQ0 Q32 15CE 12D3D0 3 14 ..
MC10153L ,Quad Latch**SEMICONDUCTOR TECHNICAL DATA* The MC10153 is a high speed, low power, MECL quad latch consisting ..
MC10153L ,Quad LatchLOGIC DIAGRAMD0 3Q02Q0G0 5DIP6Q1D1 7Q1 PIN ASSIGNMENTCE 4V V1 16CC1 CC2C 13CQ0 Q32 15CE 12D3D0 3 14 ..
MC33390 ,J-1850 Class B Serial TransceiverOrder this document by MC33390/D * The MC33390 is a serial link bus transceiver designed to provid ..
MC33390D ,Class B Serial TransceiverBlock Diagram 33390 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATAFor More Information On This Pro ..
MC33390DR2 ,Class B Serial TransceiverFeatures• Designed for SAE J-1850 Class B Data Rates• Full Operational Bus Dynamics Over a Supply V ..
MC33395DWBR2 ,Three-Phase Gate Driver ICFeaturesCASE 1324-02• Drives Six N-Channel Low R Power MOSFETsDS(ON)32-TERMINAL SOICW• Built-In Cha ..
MC33399D ,Automotive Local Interconnect Network Physical InterfaceELECTRICAL CHARACTERISTICS ( VSUP = FROM 7 TO 18V, and T FROM -40 TO 150°C UNLESS OTHERWISE NOTED) ..
MC3340P ,ELECTRONIC ATTENUATOROrder this document by MC3340/D* *The MC3340 is a simple but very effective electronic attenuator. ..
MC10141L-MC10141L.-MC10141P
Four Bit Universal Shift Register
SEMICONDUCTOR TECHNICAL DATA -
The MC10141 is a four–bit universal shift register which performs shift left, or
shift right, serial/parallel in, and serial/parallel out operations with no external
gating. Inputs S1 and S2 control the four possible operations of the register
without external gating of the clock. The flip–flops shift information on the
positive edge of the clock. The four operations are stop shift, shift left, shift right,
and parallel entry of data. The other six inputs are all data type inputs; four for
parallel entry data, and one for shifting in from the left (DL) and one for shifting
in from the right (DR).= 425 mW typ/pkg (No Load)
fShift= 200 MHz typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8 D1 D0 Q1 Q0
TRUTH TABLE*Outputs as exist after pulse appears at “C” input with input conditions as
shown. (Pulse = Positive transition of clock input).
DIP
PIN ASSIGNMENTVCC1
VEE
VCC2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
