MC10138L ,Bi-Quinary CounterLOGIC DIAGRAM PLASTIC PACKAGECASE 648–08S0 Q0 S1 Q1 S2 Q2 S3 Q311 15 10 13 6 4 5 2FN SUFFIXPLCCCASE ..
MC10138P ,Bi-Quinary CounterELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10138P ,Bi-Quinary Counter**SEMICONDUCTOR TECHNICAL DATA* *The MC10138 is a four bit counter capable of divide by two, five, ..
MC10141 ,Four Bit Universal Shift RegisterLOGIC DIAGRAMD3 D2 D1 D0DIPParallel EnterS1PIN ASSIGNMENT 1 of 4 DecoderS2Shift RightV V1 16CC1 CC2 ..
MC10141L ,Four Bit Universal Shift RegisterLOGIC DIAGRAMD3 D2 D1 D0DIPParallel EnterS1PIN ASSIGNMENT 1 of 4 DecoderS2Shift RightV V1 16CC1 CC2 ..
MC10141L. ,Four Bit Universal Shift Register**SEMICONDUCTOR TECHNICAL DATA * **The MC10141 is a four–bit universal shift register which perfo ..
MC33375ST-2.5T3 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off Control2MC33375DEFINITIONSLoad Regulation − The change in output voltage for a difference between the inpu ..
MC33375ST-5.0T3 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off ControlBlock Diagram2 7Gnd GndALYW3 6V Vin out375xxGnd Gnd4 5ON/OFF N/CThermal &Anti-satPins 4 and 5 Not C ..
MC33375ST-5.0T3 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off Control3OUTPUT VOLTAGE CHANGE (mV) OUTPUT VOLTAGE CHANGE (V)OUTPUT VOLTAGE CHANGE (mV) OUTPUT VOLTAGE CHAN ..
MC33375ST-5.0T3G , 300 mA, Low Dropout Voltage Regulator with On/Off Control
MC33385DH ,Automotive Quad Low Side DriverMAXIMUM RATINGS T = - 40 °C up to 150°CJRatings Symbols Min Max UnitSUPPLY VOLTAGEVoltage Range Vcc ..
MC33390 ,J-1850 Class B Serial TransceiverOrder this document by MC33390/D * The MC33390 is a serial link bus transceiver designed to provid ..
MC10138L-MC10138P
Bi-Quinary Counter
SEMICONDUCTOR TECHNICAL DATA-
The MC10138 is a four bit counter capable of divide by two, five, or ten
functions. It is composed of four set–reset master–slave flip–flops. Clock
inputs trigger on the positive going edge of the clock pulse.
Set or reset input override the clock, allowing asynchronous “set” or
“clear.” Individual set and common reset inputs are provided, as well as
complementary outputs for the first and fourth bits. = 370 mW typ/pkg (No Load)
ftog = 150 MHz typ
tr, tf = 2.5 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1; VCC2 = PIN 16; VEE = PIN 8 Q014
Clock
Reset Q17 Q2 Q33
COUNTER TRUTH TABLES
BI–QUINARY(Clock connected to C2
and Q3 connected to C1)
BCD(Clock connected to C1
and Q0 connected to C2)
COUNTER STATE DIAGRAM — POSITIVE LOGIC 7112 2 3 4
CLOCK CONNECTED TO C2 Q0 CONNECTED TO C2
DIP
PIN ASSIGNMENTVCC1
VEE
VCC2
RESET
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
