MC10135L ,Dual J-K Master-Slave Flip-FlopELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10136 ,Universal Hexadecimal CounterELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10136L ,Universal Hexadecimal CounterLOGIC DIAGRAMS1 9S2 7Carry In10V = PIN 1CC1V = PIN 16CC2TV = PIN 8Q0 T Q1 T Q2 Q3 EETT TTQ0 Q1 ..
MC10136P ,Universal Hexadecimal CounterELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10136P. ,Universal Hexadecimal Counter**SEMICONDUCTOR TECHNICAL DATA *The MC10136 is a high speed synchronous counter that can count up, ..
MC10137L ,Universal Decade Counter**SEMICONDUCTOR TECHNICAL DATA **The MC10137 is a high speed synchronous counter that can count up ..
MC33375D-2.5 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off ControlMC33375300 mA, Low DropoutVoltage Regulator withOn/Off ControlThe MC33375 series are micropower low ..
MC33375D-3.0 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off Controlpackages, SOT−223, and SOP−8 surface mount packages. Thesedevices feature a very low quiescent curr ..
MC33375D-3.0R2 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off ControlELECTRICAL CHARACTERISTICS (C = 1.0μF, T = 25°C, for min/max values T = −40°C to +125°C, Note 1)L A ..
MC33375D-3.3 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off ControlFeatures:12 3• Low Quiescent Current (0.3 A in OFF mode; 125 A in ON mode)V ON/OFF Vin out• Low I ..
MC33375D-3.3R2G , 300 mA, Low Dropout Voltage Regulator with On/Off Control
MC33375ST-1.8T3 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off ControlELECTRICAL CHARACTERISTICS (C = 1.0μF, T = 25°C, for min/max values T = −40°C to +125°C, Note 1)L A ..
MC10135L
Dual J-K Master-Slave Flip-Flop
LOGIC DIAGRAMVCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
S1 5
J1 7
K1 6
R1 4
C 9
S2 12
J2 10
K2 11
R2 13
SEMICONDUCTOR TECHNICAL DATA -
The MC10135 is a dual master–slave dc coupled J–K flip–flop. Asynchro–
nous set (S) and reset (R) are provided. The set and reset inputs override the
clock.
A common clock is provided with separate J–K inputs. When the clock is
static, the J–K inputs do not effect the output.
The output states of the flip–flop change on the positive transition of the
clock. = 280 mW typ/pkg (No Load)
fTog = 140 MHz typ
tpd = 3.0 ns typ
tr, tf = 2.5 ns typ (20%–80%)
R–S TRUTH TABLE CLOCK J–K TRUTH TABLE* N.D. = Not Defined *Output states change on positive
transition of clock for J–K input
condition present.
DIP
PIN ASSIGNMENTVCC1
VEE
VCC2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
