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Partno	Mfg	Dc	Qty	Available	Descript
MC10133L	MOT ?	N/a	16	avai	Quad Latch
MC10133P	MOTO	N/a	100	avai	Quad Latch
MC10133P	MOT	N/a	25	avai	Quad Latch

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MC10133L-MC10133P
Quad Latch
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8D0 2Q0G0D1CECCCED2D3
6Q1Q2Q3G1
SEMICONDUCTOR TECHNICAL DATA -
The MC10133 is a high speed, low power, quad latch consisting of four
bistable latch circuits with D type inputs and gated Q outputs, allowing direct
wiring to a bus. When the clock is high, outputs will follow D inputs. Information
is latched on the negative going transition of the clock.
The outputs are gated when the output enable (G) is low. All four latches may
be clocked at one time with the common clock (CC), or each half may be
clocked separately with its clock enable (CE). = 310 mW typ/pkg (No Load)
tpd = 4.0 ns typ
tr, tf = 2.0 ns typ (20%–80%)
TRUTH TABLE
C = CC + CE
DIP
PIN ASSIGNMENT
VCC1
VEE
VCC2

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