MC10131P ,Dual Type D Master-Slave Flip-FlopLOGIC DIAGRAMS1 5V V1 16CC1 CC2D1 7Q1 2Q2Q12 15C 6E1Q1 3 Q1 Q23 14R1 R2R1 4 4 13C 9CS1 S2 ..
MC10133L ,Quad LatchLOGIC DIAGRAMD0 3Q02Q0DIPPIN ASSIGNMENTG0 56Q1D1 7Q1CE 4 V V1 16CC1 CC2C 13 Q3Q0C 2 15CE 12D D30 3 ..
MC10133P ,Quad Latch**SEMICONDUCTOR TECHNICAL DATA* The MC10133 is a high speed, low power, quad latch consisting of f ..
MC10133P ,Quad LatchELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10134 , DUAL MULTIPLEXER WITH LATCH
MC10134L ,Dual Multiplexer With LatchLOGIC DIAGRAMV V1 16CC1 CC2A0 6Q1 Q22 15A1 11D11 4 Q1 Q23 142Q1D11 D214 13D12 5D12 D225 12CEO 103Q1 ..
MC33363P ,HIGH VOLTAGE OFF-LINE SWITCHING REGULATORELECTRICAL CHARACTERISTICS (V = 20 V, R = 10 k, C = 390 pF, C = 1.0 μF, for typical values T = 25 ..
MC33364D1R2 ,Critical Conduction GreenLine™ SMPS ControllerFeaturesx = 1 or 2• Lossless Off-Line StartupA = Assembly Location• Leading Edge Blanking for Noise ..
MC33364D2R2 ,Critical Conduction GreenLine™ SMPS Controller
MC33364D2R2 ,Critical Conduction GreenLine™ SMPS Controller2MC33364Startup circuit isStartup circuit turnscharging the VCCoff when VCC is 15Vcapacitor15VSuppl ..
MC33364D2R2 ,Critical Conduction GreenLine™ SMPS Controller3MC33364PIN DESCRIPTIONPin Function DescriptionÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1 (1) Zero Curren ..
MC33364D2R2G , Critical Conduction GreenLine TM SMPS Controller
MC10131FN-MC10131L-MC10131P
Dual Type D Master-Slave Flip-Flop
SEMICONDUCTOR TECHNICAL DATA- -
The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S)
and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip–flop
may be clocked separately by holding the common clock in the low state and
using the enable inputs for the clocking function. If the common clock is to be
used to clock the flip–flop, the Clock Enable inputs must be in the low state. In
this case, the enable inputs perform the function of controlling the common
clock.
The output states of the flip–flop change on the positive transition of the
clock. A change in the information present at the data (D) input will not affect the
output information at any other time due to master slave construction. = 235 mW typ/pkg (No Load)
FTog = 160 MHz typ
tpd = 3.0 ns typ
tr, tf = 2.5 ns typ (20%–80%)
LOGIC DIAGRAMVCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
S1 5
D1 7
CE1 6
R1 4
CC 9
R2 13
CE2 11
D2 10
S2 12
CLOCKED TRUTH TABLE R–S TRUTH TABLElowtoa high state
low to a high state. N.D. = Not Defined
DIP
PIN ASSIGNMENTVCC1
CE1
VEE
VCC2
CE2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
