MC10129L ,Quad Bus Receiver**SEMICONDUCTOR TECHNICAL DATA* The MC10129 data inputs are compatible with, and accept TTL logic ..
MC10129L ,Quad Bus ReceiverELECTRICAL CHARACTERISTICSTEST VOLTAGE VALUES (Volts)MECL 10,000 INPUT LEVELS TTL INPUT LEVELS (6.) ..
MC10131 ,Dual TYPE D Master-Slave Flip-Flop**SEMICONDUCTOR TECHNICAL DATA* * * *The MC10131 is a dual master–slave type D flip–flop. Asynchro ..
MC10131 ,Dual TYPE D Master-Slave Flip-Flop**SEMICONDUCTOR TECHNICAL DATA* * * *The MC10131 is a dual master–slave type D flip–flop. Asynchro ..
MC10131 ,Dual TYPE D Master-Slave Flip-FlopELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10131 ,Dual TYPE D Master-Slave Flip-FlopLOGIC DIAGRAMS1 5V V1 16CC1 CC2D1 7Q1 2Q2Q12 15C 6E1Q1 3 Q1 Q23 14R1 R2R1 4 4 13C 9CS1 S2 ..
MC33362DW ,HIGH VOLTAGE OFF-LINE SWITCHING REGULATORThermal Characteristics °C/WP Suffix, Dual–In–Line Case 648EÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁThermal Resis ..
MC33363ADW ,High Voltage Switching Regulatorfeatures include cycle–by–cycle current limiting, input undervoltage lockoutwith hysteresis, output ..
MC33363ADWR2 ,High Voltage Switching RegulatorELECTRICAL CHARACTERISTICS (V = 20 V, R = 10 k, C = 390 pF, C = 1.0 F, for typical values T = 25° ..
MC33363AP ,HIGH VOLTAGE OFF-LINE SWITCHING REGULATORELECTRICAL CHARACTERISTICS (V = 20 V, R = 10 k, C = 390 pF, C = 1.0 μF, for typical values T = 25 ..
MC33363AP ,HIGH VOLTAGE OFF-LINE SWITCHING REGULATORELECTRICAL CHARACTERISTICS (continued) (V = 20 V, R = 10 k, C = 390 pF, C = 1.0 F, for typical val ..
MC33363BDW ,High Voltage Switching Regulator
MC10129L
Quad Bus Receiver
LOGIC DIAGRAMVCC = PIN 9
GND = PIN 1 AND 16
VEE = PIN 8Q0D07Q1D113
3Q2D26
2Q3D34HYSTERESIS
CONTROL5
CLOCK11
RESET10
STROBE12
SEMICONDUCTOR TECHNICAL DATA -
The MC10129 data inputs are compatible with, and accept TTL logic levels
as well as levels compatible with IBM–type buses. The clock, strobe, and reset
inputs accept MECL 10,000 logic levels.
The data inputs accept the bus levels, and storage elements are provided to
yield temporary latch storage of the information after receiving it from the bus.
The outputs can be strobed to allow accurate synchronization of signals and/or
connection to MECL 10,000 level buses. When the clock is low, and the reset
input is disabled, the outputs will follow the D inputs. The latches will store the
data on the rising edge of the clock. The outputs are enabled when the strobe
input is high. Unused D inputs must be tied to VCC or Gnd. The clock, strobe,
and reset inputs each have 50 k ohm pulldown resistors to VEE. They may be
left floating, if not used.
The MC10129 will operate in either of two modes. The first mode is obtained
by tying the hysteresis control input to VEE. In this mode, the input threshold
points of the D inputs are fixed. The second mode is obtained by tying the
hysteresis control input to ground. In this mode, input hysteresis is achieved as
shown in the test table. This hysteresis is desirable where extra noise margin is
required on the D inputs. The outer input pins are unaffected by the mode of
operation used.
The MC10129 is especially useful in interface applications for central
processors, mini–computers, and peripheral equipment. = 750 mW typ/pkg (No Load)
tpd = 10 ns typ
VCC Max = 7.0 Vdc
TRUTH TABLE
PIN ASSIGNMENTGND
HYSTERESIS
CONTROL
VEE
GND
STROBE
CLOCK
RESET
VCC
