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Partno	Mfg	Dc	Qty	Available	Descript
MC10121L	MOT?	N/a	2000	avai	4-Wide OR-AND/OR-AND Gate
MC10121P	ON	N/a	5	avai	4-Wide OR-AND/OR-AND Gate
MC10121P	MOTO	N/a	475	avai	4-Wide OR-AND/OR-AND Gate
MC10121P	MOTOROLA	N/a	12	avai	4-Wide OR-AND/OR-AND Gate
MC10121P	MOT	N/a	13	avai	4-Wide OR-AND/OR-AND Gate

MC10121L ,4-Wide OR-AND/OR-AND GateLOGIC DIAGRAMCASE 775–02456 DIPPIN ASSIGNMENT79V V1 16CC1 CC22103A4A 2 15INOUT11 A A43 14OUT IN12A1 ..
MC10121P ,4-Wide OR-AND/OR-AND GateLOGIC DIAGRAMCASE 775–02456 DIPPIN ASSIGNMENT79V V1 16CC1 CC22103A4A 2 15INOUT11 A A43 14OUT IN12A1 ..
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MC10121L-MC10121P
4-Wide OR-AND/OR-AND Gate
SEMICONDUCTOR TECHNICAL DATA-
The MC10121 is a basic logic building block providing the simultaneous
OR–AND/OR–AND–Invert function, useful in data control and digital multiplexing
applications. = 100 mW typ/pkg (No Load)
tpd = 2.3 ns typ
tr, tf = 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
A1IN
A1IN
A1IN
A2IN
VEE
VCC2
A4IN
A4IN
A4IN
A3IN
A3IN
A2IN, A3IN
A2IN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).

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