MC10114 ,Triple Line Receiver**SEMICONDUCTOR TECHNICAL DATA** * * The MC10114 is a triple line receiver designed for use in sens ..
MC10114FN ,Triple Line ReceiverELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10114L ,Triple Line ReceiverLOGIC DIAGRAMA C4 13IN INA C5 12IN IN4 25 3VB 6 11BBOUT9 6B 7 10 BOUT IN10 7V B8 9EE IN12 1413 15Pi ..
MC10114P ,Triple Line ReceiverLOGIC DIAGRAMA C4 13IN INA C5 12IN IN4 25 3VB 6 11BBOUT9 6B 7 10 BOUT IN10 7V B8 9EE IN12 1413 15Pi ..
MC10115 ,Quad Line ReceiverELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10115L ,Quad Line ReceiverLOGIC DIAGRAM42DIP5PIN ASSIGNMENT736V 1 16 VCC1 CC2101411 A D2 15OUT OUTB C13 3 14OUT OUT1512A 4 13 ..
MC33272ADR2G , Single Supply, High Slew Rate, Low Input Offset Voltage Operational Amplifiers
MC33272AP ,HIGH PERFORMANCE OPERATIONAL AMPLIFIERSOrder this document by MC33272A/D* " * * * ! *HIGH PERFORMANCE**! * * ** **OPERATIONAL* ** *AMPLI ..
MC33274 ,HIGH PERFORMANCE OPERATIONAL AMPLIFIERSMAXIMUM RATINGSRating Symbol Value UnitSupply Voltage V to V +36 VCC EEInput Differential Voltage R ..
MC33274 ,HIGH PERFORMANCE OPERATIONAL AMPLIFIERSMAXIMUM RATINGSRating Symbol Value UnitSupply Voltage V to V +36 VCC EEInput Differential Voltage R ..
MC33274AD ,Single Supply, High Slew Rate, Low Input Offset Voltage, Quad Op AmpMAXIMUM RATINGSRating Symbol Value UnitSupply Voltage V to V +36 VCC EEInput Differential Voltage R ..
MC33274ADR2 ,Single Supply, High Slew Rate, Low Input Offset Voltage, Quad Op AmpMC33272A, MC33274A,NCV33274ASingle Supply,High Slew Rate,Low Input Offset Voltage
MC10113FN-MC10113L-MC10113P
Quad Exclusive OR Gate
LOGIC DIAGRAMVCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 89 15 14 3 2
SEMICONDUCTOR TECHNICAL DATA -
The MC10113 is a quad Exclusive OR gate, with an enable common to all
four gates. The outputs may be wire–ORed together to perform a 4–bit
comparison function (A = B). The enable is active low. = 175 mW typ/pkg (No Load)
tpd = 2.5 ns typ
tr, tf = 2.0 ns typ (20% to 80%)
TRUTH TABLE
DIP
PIN ASSIGNMENTVCC1
AOUT
BOUT
AIN
AIN
BIN
BIN
VEE
VCC2
DOUT
COUT
DIN
DIN
CIN
CIN
ENABLE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
