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MC100LVEL92DWR2
5V Triple PECL Input to LVPECL Output Translator
MC100LVEL92
5V�Triple PECL Input to
LVPECL Output T ranslator
The MC100LVEL92 is a triple PECL input to LVPECL output
translator. The device receives standard PECL signals and translates
them to differential LVPECL output signals.
To accomplish the PECL to LVPECL level translation, the
MC100LVEL92 requires three power rails. The VCC supply is to be
connected to the standard 5 V PECL supply, the LVCC supply is to be
connected to the 3.3 V LVPECL supply, and Ground is connected to
the system ground plane. Both the VCC and LVCC should be bypassed
to ground with 0.01 �f capacitors.
The PECL VBB pin, an internally generated voltage supply, is
available to this device only. For single-ended input conditions, the
unused differential input is connected to VBB as a switching reference
voltage. VBB may also rebias AC coupled inputs. When used,
decouple VBB and VCC via a 0.01 �F capacitor and limit current
sourcing or sinking to 0.5 mA. When not used, VBB should be
left open. 500 ps Propagation Delays 5 V and 3.3 V Supplies Required ESD Protection: Human Body Model; >2 kV,
Machine Model; >200 V The 100 Series Contains Temperature Compensation LVPECL Operating Range: LVCC = 3.0 V to 3.8 V PECL Operating Range: VCC = 4.5 V to 5.5 V Internal Input Pulldown Resistors Q Output will Default LOW with Inputs Open or < GND + 1.3 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index 28 to 34 Transistor Count = 247 devices Pb−Free Package is Available*
http://*For additional marking information, refer to
Application Note AND8002/D.
MARKING DIAGRAM* = Assembly Location = Wafer Lot = Year = Work Week
SO−20 WB
DW SUFFIX
CASE 751DSee detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
