MC100LVEL90 ,Triple ECL to PECL translator
MC100LVEL90DW ,Triple ECL to PECL Translator
MC100LVEL90DW ,Triple ECL to PECL Translator
MC100LVEL90DWR2 ,-3.3V/-5V Triple ECL Input to LVPECL Output TranslatorAN1672/DThe ECL Translator GuidePECL • LVPECL • NECL • TTL •LVTTL/LVCMOS • CMOS
MC100LVEL91 ,3.3V/5V Triple LVPECL / PECL Input to -3.3V ECL Output Translator2AN1672/DSection 1: Translation Between Differently Supplied ECL Drivers and ReceiversTable 3. Tran ..
MC100LVEL91 ,3.3V/5V Triple LVPECL / PECL Input to -3.3V ECL Output Translator
MC33201 ,Amplifiers and Comparators
MC33201D ,Low Voltage, Rail-to-Rail, Single Operational AmplifierELECTRICAL CHARACTERISTICS (V = + 5.0 V, V = Ground, T = 25°C, unless otherwise noted.)CC EE ACha ..
MC33201DR2 ,Low Voltage, Rail-to-Rail, Single Operational AmplifierELECTRICAL CHARACTERISTICS (V = + 5.0 V, V = Ground, T = 25°C, unless otherwise noted.)CC EE ACh ..
MC33201DR2 ,Low Voltage, Rail-to-Rail, Single Operational AmplifierELECTRICAL CHARACTERISTICS (V = + 5.0 V, V = Ground, T = 25°C, unless otherwise noted.)CC EE ACh ..
MC33201DR2 ,Low Voltage, Rail-to-Rail, Single Operational Amplifierhttp://onsemi.comThe MC33201/2/4 family of operational amplifiers providerail−to−rail operation on ..
MC33201DR2G , Low Voltage, Rail−to−Rail Operational Amplifiers
MC100LVEL90
Triple ECL to PECL translator
SEMICONDUCTOR TECHNICAL DATA --
The MC100LVEL/EL90 is a triple ECL to PECL translator. The device
receives either standard or low voltage differential ECL signals and
translates them to either standard or low voltage differential PECL output
signals. The LVEL device can handle the low voltage signals while the EL
device is designed for the standard signals. It is possible to have low
voltage signals on one side and standard signals on the other if the
LVEL90 is used. 500ps Propagation Delays Fully Differential Design Supports both Standard and Low Voltage Operation 20–Lead SOIC Packaging
A VBB output is provided for interfacing with single ended ECL signals
at the input. If a single ended input is to be used the VBB output should be
connected to the D input. The active signal would then drive the D input.
When used the VBB output should be bypassed to ground via a 0.01μF
capacitor. The VBB output is designed to act as the switching reference
for the EL90 under single ended input switching conditions, as a result
this pin can only source/sink up to 0.5mA of current.
To accomplish the level translation the EL/LVEL90 requires three
power rails. The VCC supply should be connected to the positive supply,
and the VEE pin should be connected to the negative power supply. The
GND pins as expected are connected to the system ground plain. Both
VEE and VCC should be bypassed to ground via 0.01μF capacitors.
Under open input conditions, the D input will be biased at VEE/2 and
the D input will be pulled to VEE. This condition will force the Q output to a
LOW, ensuring stability.D1
Logic Diagram and Pinout: 20-Lead SOIC (Top View) Q1 Q2 Q2 VCC
VCC Q0 D2VCC VEE
GND
VBB
GND
VBB
PIN NAMES
